本論文為基於元件的嵌入式系統設計提出一套整合性的模型。
現今的系統模型並不適用於所有的設計方式，例如：合成式的設計方式使用的是高階模型而在一般的手動的硬體設計方式則是使用低階的電路圖。

雖然高階系統合成有望能排除大部份的低階錯誤，但是該模型無法允許工程師介入低階的設計決定，導致這種設計方式現在不被廣泛使用。現今的電路設計方式是由工程師手動畫出高階方塊圖，並摻入一些低階的機制， 做為滿足來自其他設計面向的約束手段，例如機構設計，安全法規，備料成本等等不同領域。 但是，如此設計出來的系統，即使小修改都容易改錯且維護困難，主要是因為設計師很難把用意表達為機器能理解的形式。

為了解決這個問題， 我們提出一個基於標籤的方塊圖模型。這種模型不僅可以表達最高階的系統結構，也能表達最低階電路圖的概念。 我們認為方塊圖本身並不具備意義，它的意義是由人所賦予的。透過顏色或形狀我們可以給予不同的方塊圖添加含義，而本篇論文選擇的方式是透過標籤的方式來讓方塊圖不再只有形狀而是有更多的意義。

除了一般的方塊圖，我們的系統還有一個元件庫，用來讓使用者挑選要使用什麼元件實作。我們定義每一個元件是一個有實作標籤集合的包裝， 並且只要某個方塊被貼上的標籤集合是某個元件的標籤集合的子集合， 該元件就能成為該方塊的實作候選元件。 我們也把這個概念延伸到方塊圖上的其他元素，包含方塊上的埠，埠與埠之間的連接器，以及連接器的多個插座。 如此一來， 只要使用者根據不同層的需求去貼標籤， 我們的設計系統就會確保標籤之間的關係都能成立。

本論文將上述的標籤式方塊圖套用於兩個設計階段：元件挑選和介面完成，並選用一個實際設計的電路圖做為說明本設計方法細節的實例。 實驗結果顯示，我們提出的模型不僅能夠以直觀的方式捕捉系統結構， 更重要的是能在允許手動介入低階機制的前提下，有效的支援設計空間探索。 本研究預期能成為下一代設計工具的核心技術，讓工程師能以此整合性模型捕捉到設計的用意與獲得設計上的輔助。

This thesis proposes a unified model from block diagrams to schematics for component-based design of embedded systems. Today, there exists a dichotomy between high-level models for synthesis or low-level schematics. Although synthesis approaches promise elimination of many low-level errors, their inability to accommodate manual intervention at the low level precludes their use in most designs. In practice, today's engineers craft the low-level schematic by manually converting a block diagram that is mostly high level but mixed in with low-level mechanisms. Low-level intervention is necessary in order to satisfy constraints from mechanical design, safety regulations, material cost, and many other domains. Unfortunately, such a design methodology results in designs that tend to be fragile and difficult to maintain, as the intent of the mechanism is not captured in any machine-readable form.

To address this problem, we propose a tag-based block diagram for representing the system architecture from the highest-level block diagram down to the lowest-level schematic. The idea is that a block is just a drawing unless injected with tags, which are tokens of intent, and components that self-declare to implement the tags become candidates for implementation of the block. The concept is generalized to the ports on the blocks, the links that connect the blocks, and the slots on the links. Thus, the user can tag each design object to be as high or as low level as needed, and our system propagates these tags to ensure all relations among them hold.

This thesis describes the use of this tag-based block diagram in two stages of the design flow, namely component selection and interface completion. We illustrate the detailed transformation of this model using a real-life reference design as our case study. The results show that our proposed model is able to not only capture the system architecture in an intuitive and expressive way, but more importantly support effective design space exploration (DSE) while allowing manual interventions. This work is a core technology that is expected to empower the next-generation design tool that allows practicing designers to capture their design intent and mechanisms in a unified model.

Contents i
Acknowledgments vi
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Related Work 4
2.1 Interface Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.1 MCU-Peripheral Interface Synthesis . . . . . . . . . . . . . . . . . . . . . . 4
2.1.2 Communication Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.3 Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.4 Bus Interface Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Printed Circuit Board Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 Academic Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.2 Graphical Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Hardware Description Languages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Architecture Description Language . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Design Concepts 11
3.1 Component vs. Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.1 Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.2 Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.1 Linkcomp and Slotcomp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.2 Linkblock and Slotblock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Basic Tagging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1 Taggable and Untaggable Objects . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.2 Effect of Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.1 Portcomps vs. Pincomps . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.2 Linkcomps vs. Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.3 Portblocks and Linkblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5 Inter-Tag Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5.1 Grouping vs. Mutual Exclusion . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5.2 Illustrative Example of Entanglements . . . . . . . . . . . . . . . . . . . . . 20
3.6 Attributes and Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6.1 Component Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6.2 Block Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6.3 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7 Design Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7.1 Top-Down Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7.2 Low-level Intervention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4 Technical Approach 25
4.1 Block-Oriented Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.1 Block Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.2 Algorithm for Linkblock Refinement . . . . . . . . . . . . . . . . . . . . . . 27
4.2 Link-Oriented Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3 Design with Low-level Intervention . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5 Implementation 33
5.1 Prototype System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2.1 Macro Prefix (#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2.2 Up-Directory (../) and Exclusion (ˆ) . . . . . . . . . . . . . . . . . . . . . . 36
5.2.3 Macro Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6 Case Study: CC2650 Remote Control 38
6.1 Component Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.1 Case Study: CC2650 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.2 Tagset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1.3 Portcomps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1.4 Pincomps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.2 Link Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3 System Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.1 IMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.2 LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.3.3 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7 Conclusions and Future Work 49
7.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.2.1 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.2.2 Tag System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Appendix 54

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