隨著技術節點的發展迅速，標準元件的不同版本之間的高度允許存在非整數倍數關係。對於一個標準元件，較大的面積有較大的驅動強度、較小的延遲時間、較好的引腳存取性;而較小的面積有較小的功耗，對於非關鍵路徑上的元件，較小面積的版本可以同時節省設計面積和耗能，此種非整數倍數稱為非整數倍數混合元件高度設計對於效能、功耗以及面積都有更優秀的解答空間，因此，非整數倍數高度電路近年來在實體設計中擁有很大的研究價值。

相較於傳統單一列高設計，擺置區域的列不再只有一種高度，而決定某個高度的列需要多少數量，以及座落的位置，就變得相當的重要。
在合法化階段，規範每個標準元件必須位於與自己高度相符的列，並且元件之間不能發生重疊，而一個不理想的列配置會導致標準元件平均位移很大，進而影響總線長，最終使得電路效能變差。

本篇論文會先預估不同高度的列各需要的數量，並修改元件庫內的高度使電路可以使用現有的商用工具來完成配置和時鐘樹合成，在基於動態規劃的演算法下，電路可以獲得很好的列配置，並基於Abacus\cite{abacus}演算法來合法化電路，最後再用商用工具來完成繞線。實驗結果顯示本篇論文相較以往的研究可以獲得更短的線長、更低的耗能以及更好的電路效能。

With the rapid development of technology nodes, the heights between different versions of a standard cell can be non-integer multiples. A design with non-integer multiple-cell-height(NIMCH) has larger solution space to optimize performance, power consumption, and area. A larger cell has greater driving strength, less delay time, and better pin accessibility, while a smaller cell has less power consumption. For cells on non-critical paths, the smaller cell can save design area and power consumption at the same time.
Compared with the traditional single-row height design, the rows in the placement area no longer have only one height. Thus, it becomes crucial to determine the number of rows of a certain height and their locations. In the legalization stage, it is specified that each standard cell must be located in a row that matches its height and there should be no overlap between cells. An unideal row configuration
will result in sizeable average cell displacements, increasing wirelength, and ultimately degrading circuit performance.
This thesis will first estimate the required number of rows of different heights, and modify heights in the cell library so that the design can use the existing commercial tools to complete the placement and clock tree synthesis. Then, under the algorithm based on dynamic programming, the chip design can get an excellent row configuration, legalize the circuit based on the Abacus\cite{abacus} algorithm, and complete the routing with commercial tools. The experimental results show that this thesis can achieve smaller wire lengths, lower power consumption, and better circuit performance than previous studies.

誌謝
摘要i
Abstract ii
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Previous Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Preliminaries 5
2.1 Row and Cell Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Proposed Approach 7
3.1 Overall Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Initial Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Row Configuration Generation . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4 Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5 Worst-Case Computational Complexity . . . . . . . . . . . . . . . . . . . . . 16
3.6 Legalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Experimental Results 19
4.1 Environment and Cell Library Creation . . . . . . . . . . . . . . . . . . . . . 19
4.2 Benchmark Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 Conclusion 29
Bibliography 31

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