多位元正反器通常用於減少時鐘接收器的數量，從而實現低功耗設計。傳統的 多位正反器由具有相同驅動強度的單位元正反器所組成。但是，如果多位元正反器中僅有一些位元違反時序約束，則必須調整多位元正反器 的大小或將其分解為更小的位寬組合以滿足時序，這將會降低省電的比率。
在本文中，我們提出了一種新的多位元正反器生成方法，該方法考慮了混合驅動多位元正反器，其某些位元具有比其他位元更高的驅動強度。為了最大化正反器的合併率（最小化時鐘接收器的最終數量），我們的方法將首先在時序約束下執行激進的正反器合併。從某種意義上說，我們的合併是激進的，是因為我們可能會願意加大一些正反器的尺寸，以便盡可能地將正反器合併到具有相同驅動強度的多位元正反器中。
過大的多位元正反器將在之後的階段在時序限制下而縮小，最終產生混合驅動的多位元正反器。
此外，正反器們通過對齊的方法重新定位，以利用水平長時鐘引腳形狀來減少時鐘線長度，從而進一步降低時鐘功率。
我們的生成方法已與商業佈局和佈線工具相結合，實驗結果表明，我們的方法在時鐘接收器的數量、正反器功率、時鐘緩衝器的數量以及時鐘樹線長優於僅考慮相同驅動多位元正反器的先前工作。

Multi-bit flip-flops (MBFFs) are often used to reduce the number of clock sinks, resulting in a low-power design. A traditional MBFF is composed of individual FFs of uniform driving strength. However, if some but not all of the bits of an MBFF violate timing constraints, the MBFF has to be sized up or decomposed into smaller bit-width combinations to satisfy timing, which reduces the power saving. In this paper, we present a new MBFF generation approach considering mixed-driving MBFFs whose certain bits have a higher driving strength than the other bits. To maximize the FF merging rate (and hence to minimize the final amount of clock sinks), our approach will first perform aggressive FF merging subject to timing constraints. Our merging is aggressive in the sense that we are willing to possibly oversize some FFs in order to merge FFs into MBFFs of uniform driving strengths as much as possible. The oversized individual FFs of an MBFF will be later downsized subject to timing constraints by our approach, which results in a mixed-driving MBFF. Moreover, FFs and MBFFs are relocated through an alignment method to take advantage of the horizontal long clock pin shapes to reduce the clock wirelength for further clock power reduction. Our MBFF generation approach has been combined with a commercial place and route tool, and our experimental results show the superiority of our approach over a prior work that considers uniform-driving MBFFs only in terms of the clock sink count, the FF power, the clock buffer count, the routed clock wirelength, and the clock capacitance.

誌謝
摘要 i
Abstract ii
1 Introduction 1
1.1 Multi-bit Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Previous Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Preliminaries 7
2.1 MBFF Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Flip Flop Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Proposed Approach 9
3.1 Overall Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Compute Feasible Regions of Flip Flop . . . . . . . . . . . . . . . . . . . . . 11
3.3 Find all Maximal Cliques in Multiple Rectangle Intersection Graphs . . . . . . 12
3.4 Non-Conflicting MBFFs Generation . . . . . . . . . . . . . . . . . . . . . . . 13
3.5 Flip-Flop Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6 Timing-Driven MBFF Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4 Experimental Results 23
4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 Comparison with Mean Shift [1] . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.1 The Results of Clock Sink Count, FF Area, and FF Power . . . . . . . 24
4.2.2 Clock Tree Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . 25
4.3 Limited Selection of Mixed-Driving MBFFs . . . . . . . . . . . . . . . . . . . 27
4.4 Considering Signal Switching Power . . . . . . . . . . . . . . . . . . . . . . . 30
5 Conclusion 33
Bibliography 35

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