現今的嵌入式硬體設計是由電路圖(Schematic)和 PCB 布局(PCB layout)文件的形式來進行的。我們可以將電路圖視為類似「原始碼」，並在上面進行修改來修復錯誤及進一步地設計。然而，由於缺乏了需求以及元件模型，導致這樣的設計變得脆弱且不完整，即使再小的修改都有可能導致設計失去功能，如此工程師無法有效率地進行設計。
為了解決這個問題，本論文提出了一套設計工具，可以將低階電路圖轉換為高階方塊圖，以幫助理解並進行更有效的修改。我們提出了一個類似子圖同構的演算法來提取補
丁(Patch)，即由元件和其被動元件所組成的子電路。接著，我們基於標籤式的元件模型，可以根據標籤集之間的交集來推斷出更高階的方塊圖。由於我們的工具可以根據原始設計的意圖來對後續的修改做檢查，因此所產生的方塊圖不僅可讀性高，在修改的時候也更加穩健且可靠。

Today’s embedded hardware designs are captured in the form of a schematic diagram along with a PCB layout file. The schematic could be viewed analogous to the “source code” on which modifications could be made for bug fixes and design evolution. However, the lack of requirements and lack of component models mean such a design representation is brittle, as a slight modification could render the design nonfunctional.
To address this problem, this thesis proposes a tool that converts the low-level schematic to a higher-level block diagram to aid understanding and more robust modification. We propose a sub-graph isomorphism algorithm that extracts the patches, namely subcircuits consisting of components and supporting passive elements. Then, our tag-based component model enable higher-level block diagrams to be inferred based on intersections of the tagsets. The resulting block diagrams are not only easier to understand by humans but are also more robust to modify, as the tool can check modifications against the original design intent.

Contents i
Acknowledgments vi
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Background and Related Work 4
2.1 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.1 Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.2 Textual Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.3 SKiDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.4 SchemDraw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Bottom-up Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 Netlist Transformation and Visualization . . . . . . . . . . . . . . . . . . . 7
2.2.2 Subgraph Isomorphism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Problem Statement 9
3.1 Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.2 Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Design by Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.1 Taggable Blocks and Portblocks . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.2 Components and Portcomps . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.3 Port Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.4 Links and Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Problem Formulation 15
4.1 Hypergraph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Block Diagram as a Quadpartite Graph . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Schematic as a Tripartite Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 Graph Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Technical Approach 18
5.1 Netlist Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 Patch Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.1 Component Preprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.2 Net Traversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.3 Graph Merging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3 Unrefinement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.1 Pins Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.2 Link Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.4 Retagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6 Case Study 31
6.1 EcoMini . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2 System Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2.1 Component Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.2 Link Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3 Conversion from Schematic to Block Diagram . . . . . . . . . . . . . . . . . . . . . 34
6.3.1 Conversion from Netlist to Graph . . . . . . . . . . . . . . . . . . . . . . . 34
6.3.2 Patch Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.3 Unrefinement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7 Conclusions and Future Work 40
7.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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