近似計算是一種針對可容忍錯誤之應用的新興設計技術，它可以透過換取電路的正確性來改善電路的面積、延遲或功耗。我們於此論文提出一種基於基因演算法的近似邏輯合成方法，該方法在保證錯誤率的情況下顯著地減少了電路的面積及深度。我們在IWLS2005和MCNC的電路上進行實驗，實驗結果顯示在5%的錯誤率限制下，我們提出的方法能夠減少多達80%的面積和50%的深度。與最新的方法相比，我們提出的方法在相同的5%錯誤率限制下平均能夠多減少11%的面積和188%的深度。

Approximate computing is an emerging design technique for error-tolerant applications, which may improve circuit area, delay, or power consumption by trading off a circuit's correctness. In this paper, we propose a novel approximate logic synthesis approach based on genetic algorithm, and the approach significantly reduces circuit sizes and depths with an error rate guarantee. We conduct experiments on a set of IWLS 2005 and MCNC benchmarks. The experimental results demonstrate that the area and depth can be reduced by up to 80% and 50% under a 5% error rate constraint, respectively. As compared with the state-of-the-art method, our approach can achieve an average of 11% more area savings and 188% more depth reduction under the same 5% error rate constraint.

中文摘要
Abstract
Acknowledgement
Contents
List of Tables
List of Figures
1 Introduction 1
2 Preliminaries 3
2.1 Error Metrics 3
2.2 And-Inverter-Graphs 3
2.3 Genetic Algorithm 4
3 Proposed Approach 5
3.1 Node to Constant 5
3.2 Circuit Partitioning 6
3.3 Genetic Algorithm Design 7
3.4 Subcircuit Selection and Combination 15
3.5 Overall Flow 17
4 Experimental Results 19
5 Conclusion 25

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