本論文設計一個應用在高速資料傳輸的類比式時脈資料回復電路，並具有1:8解串器將資料做取樣和並行化，供後續系統使用。
這個類比式時脈回復電路主要組成的電路有全速率相位偵測器、頻率偵測器、電荷幫浦、迴路濾波器、壓控振盪器、電壓比較器和模式控制器。在設計上壓控振盪器有16條頻帶可以選擇，頻率可調範圍為15GHz~17.3GHz，操作上，頻率偵測器會先判斷資料傳輸速率位於哪條頻帶內，再由相位偵測器完成時脈鎖定。最後鎖定的時脈經過除頻器產生解串器需要頻率，完成對資料的取樣和產生並行數據。
這個操作在16Gb/s的類比式時脈資料回復電路與解串器使用TSMC 65nm製程設計與驗證，操作電壓1.2V，輸入資料為16Gb/s PRBS31，差動訊號振幅0.6V，還原時脈速率為16GHz，輸出資料速率為2Gb/s，模擬結果時脈峰對峰抖動為3.05ps，輸出資料時脈峰對峰抖動為3.68ps，功耗為82.8mW，電路面積為516.145um×338.795um。

In this paper, an analog clock data recovery circuit is designed for high-speed data transmission, and a 1:8 deserializer is used to sample and parallelize the data for subsequent systems.
The main circuits of this analog clock recovery circuit are full-rate phase detector, frequency detector, charge pump, loop filter, voltage controlled oscillator, voltage comparator, and Mode controller. In the design, the voltage controlled oscillator has 16 frequency bands to choose from, the frequency adjustable range is 15GHz~17.3GHz. In operation, the frequency detector will first determine which frequency band the data transmission rate is in, and then the phase detector completes the clock locking. Finally, the locked clock passes through the divider to generate the frequency required by the deserializer, complete the sampling of the data, and generate parallel data.
This analog clock data recovery circuit and deserializer operating at 16Gb/s is designed and verified using TSMC 65nm process. The operating voltage is 1.2V, the input data is 16Gb/s PRBS31, the differential signal amplitude is 0.6V, the reduction rate is 16GHz, the output data rate is 2Gb/s, the analog results are clock peak-to-peak clock jitter of 3.05ps, the output data peak-to-peak clock jitter of 3.68ps, the power consumption is 82.8mW, and the circuit area is 516.145um×338.795um.

摘要 i
Abstract ii
目錄 iii
圖目錄 v
表目錄 x
第一章 緒論 1
1.1 簡介 1
1.2 論文章節介紹 2
第二章 時脈資料回復電路與解串器介紹 3
2.1 有線傳輸系統簡介 3
2.2 時脈資料回復電路基本架構及操作原理 5
2.2.1 相位偵測器 5
2.2.2 電荷幫浦 10
2.2.3 迴路濾波器 11
2.2.4 壓控振盪器 12
2.3 性能指標與其他時脈資料回復電路種類 19
2.3.1 性能指標 19
2.3.2 其他時脈資料回復電路種類 22
2.4 解串器 26
2.4.1 1:2解串器 27
2.4.2 1:4解串器 28
第三章 電路設計與實現 30
3.1 電路架構 30
3.2 相位偵測器 31
3.2.1 架構選擇 31
3.2.2 電路實現 32
3.3 頻率偵測器 35
3.3.1 判斷頻率鎖定電路 36
3.3.2 相位頻率偵測器 39
3.3.3 頻率偵測器 41
3.4 電荷幫浦 42
3.5 壓控振盪器 46
3.5.1 電路架構 46
3.5.2 可變電容 47
3.5.3 切換式電容陣列 48
3.5.4 相位雜訊 51
3.5.5 時脈緩衝器 54
3.5.6 模擬結果 55
3.6 迴路濾波器 58
3.7 比較器 62
3.8 模式控制器 64
3.9 除頻器 65
3.10 解串器 66
第四章 佈局規劃與系統迴路模擬結果 68
4.1 電路佈局 68
4.2 系統迴路模擬 70
第五章 結論 86
參考文獻 87

[1]SHF Communication Technologies AG, “Application note AN-jitter-l-jitter analysis using SHF 10000 series bit error rate testers,” 2005.
[2]劉深淵, 楊清淵, 鎖相迴路, 滄海書局, 2006.
[3]A. Amirkhany, "Basics of Clock and Data Recovery Circuits: Exploring High-Speed Serial Links," in IEEE Solid-State Circuits Magazine, vol. 12, no. 1, pp. 25-38, Winter 2020.
[4]Behzad Razavi, Design of integrated circuit for optical communication. New York: McGraw-Hill, 2003.
[5]C. R. Hogge, “A Self-correcting clock recovery circuit,” IEEE J. Lightwave Tech., vol. 3, pp. 1312-1314, Dec. 1985.
[6]J. D. H. Alexander, “Clock recovery from random binary data,” Electronics Letters, vol. 11, pp. 541-542, Oct. 1975.
[7]高耀煌, 射頻鎖相迴路IC設計, 滄海書局, 2005.
[8]Behzad Razavi, Design of analog CMOS integrated circuits, McGraw-Hill, 2001.
[9]Tektronix, “時序水平抖動的認識和特性分析”.
[10]J. C. Scheytt, G. Hanke, and U. Langmann, “A 0.155, 0.622, and 2.488 Gb/s automatic bit rate selecting clock and data recovery IC for bit rate transparent SDH systems,” ISSCC Dig. of Tech. Papers, pp. 348-349, Feb. 1999.
[11]W.-Y. Lee, K.-D. Hwang, and L.-S. Kim, “A 5.4/2.7/1.62-Gb/s receiver for DisplayPort version 1.2 with multi-rate operation scheme,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 12, pp. 2858-2866, Nov. 2012.
[12]D. Dalton, K. Chai, E. Evans, M. Ferriss, D. Hitchcox, P. Murray, S. Selvanayagam, P. Shepherd, and L. DeVito, “12.5-Mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2713-2725, Dec. 2005.
[13]X. Maillard, F. Devisch, and M. Kuijk, “A 900-Mb/s CMOS data recovery DLL using half-frequency clock, “ IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 711-715, jun. 2002.
[14]Ruiyuan, and G. S. La Rue,”Fast acquisition clock and data recovery circuit with low jitter,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1016-1024, May. 2006.
[15]Jeff L. Sonntag and John Stonick, ”A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links,” IEEE J. Solid-State Circuits, vol. no. 8, pp. 1867-1875, Aug. 2006.
[16]F. Tobajas, R. Esper-Chain, R. Regidor, O. Santana and R. Sarmiento, "A Low Power 2.5 Gbps 1:32 Deserializer in SiGe BiCMOS Technology," 2006 IEEE Design and Diagnostics of Electronic Circuits and systems, Prague, Czech Republic, 2006, pp. 19-24.
[17]S. -H. Lin and S. -I. Liu, "Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 55, no. 12, pp. 1214-1218, Dec. 2008.
[18]P. Andreani, Xiaoyan Wang, L. Vandi and A. Fard, "A study of phase noise in colpitts and LC-tank CMOS oscillators," in IEEE Journal of Solid-State Circuits, vol. 40, no. 5, pp. 1107-1118, May 2005.
[19]Jri Lee, K. S. Kundert and B. Razavi, "Analysis and modeling of bang-bang clock and data recovery circuits," in IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1571-1580, Sept. 2004.