科技不斷進步，通訊市場對於傳輸速率的要求也越來越高，行動通訊系統一路發展到現今的5G甚至6G，使得頻寬的需求日益提升。而通訊市場的蓬勃發展，除了對於速度的需求，操作的頻段也必須有所管控，利用鎖相迴路來產生精準的本地震盪頻率作為升降通訊頻率之用途，現今鎖相迴路扮演著重要的角色。
全數位式鎖相迴路與傳統類比式以及數位式鎖相迴路相比，具有更佳的雜訊容忍度，而隨著製成不斷的發展，在電路的設計上更容易隨著製程一起縮小面積，不同製程重新設計的心力也大幅減少。
本論文提出之全數位鎖相迴路為操作在6.4GHz並應用於有線通訊，相位偵測器採用二元相位偵測器，偵測參考訊號以及震盪器經過除頻器訊號之相位差，鎖定時間較長，但面積與功耗相對較小。
數位濾波器由一階類比式RC濾波器轉換而來，取代電容電阻大幅降低晶片之面積，此外在數位濾波器中加入scan chain電路，除了能夠觀測與測試邏輯電路，還能直接輸入系統設計所預期之電壓，大幅加快所相迴路之鎖定時間。
數位控制震盪器提供6.23GHz至6.65GHz的操作範圍，由切換式電容來調變電容電感震盪器的震盪頻率範圍，透過上述子電路建構出完正整的全數位鎖相迴路。
本論文採用台積電65奈米製程技術進行模擬設計，論文的開頭先簡介各種鎖相迴路的架構並比較其優劣，接著依序介紹全數位所相迴路之數學模型以及設計之流程並進行子電路雜訊分析，接續是實際電路模擬結果以及晶片模擬布局考量，最後對於提出之所相迴路做出統合結論

With the continuous advancement of technology, the communication market has more and more requirements for transmission rates. The development of mobile communication systems all the way to today’s 5G or even 6G has increased the demand for bandwidth. Also, with the booming development of the communication market, besides to the demand for speed, the frequency band of operation must also be controlled carefully. The phase-locked loop is used to generate accurate local oscillation frequency for the purpose of raising and lowering the communication frequency. The phase-locked loop plays an important role nowadays.
Compared with traditional analog and digital phase-locked loops, the fully digital phase-locked loop has better noise tolerance, and with the continuous development of manufacturing, it is easier to reduce the area of the circuit design along with the process. , the effort to redesign different processes is also greatly reduced.
The all-digital phase-locked loop proposed in this paper operates at 6.4GHz and is applied to wired communication. The phase detector uses a binary phase detector to detect the phase difference between the reference signal and the oscillator signal after passing through the frequency divider. Although the locking time longer, the area and power consumption are relatively small.
The digital filter is converted from a first-order analog RC filter, which greatly reduces the area of the chip by replacing the capacitor and resistor. In addition, adding a scan chain circuit to the digital filter can not only observe and test the logic circuit, but also directly input the expected voltage to the system, greatly accelerates the locking time of the phase loop.
This paper adopts TSMC's 65nm process technology for simulation and design. At the beginning of the paper, the architecture of various phase-locked loops is introduced and their advantages and disadvantages are compared, and then the mathematical model and design process of all-digital phase-locked loops are introduced in sequence. Next, the noise of sub-circuits are analyzed, followed by the actual circuit simulation results and chip simulation layout considerations. Finally, make a unified conclusion about the proposed circuit.

摘要 i
Abstract ii
目錄 iv
圖目錄 vii
表目錄 xi
1 第一章 緒論 1
1.1 研究動機 1
1.2 章節介紹 2
2 第二章 傳統鎖相迴路基本介紹 3
2.1 簡介 3
2.2 鎖相迴路基本原理 3
2.2.1 相位頻率偵測器 4
2.2.2 電流幫浦 7
2.2.3 迴路濾波器 8
2.2.4 壓控震盪器 12
2.2.5 除頻器 17
2.3 鎖相迴路系統雜訊與穩定度分析 18
2.3.1 傳統鎖相回路訊分析 18
2.3.2 傳統鎖相回路穩定性分析 20
3 第三章 全數位鎖相迴路系統 22
3.1 全數位鎖相迴路架構 22
3.1.1 簡介 22
3.1.2 二元相位偵測器(Bang Bang Phase Detector) 23
3.1.3 數位濾波器 24
3.1.4 數位控制震盪器 26
3.2 非線性全數位二元相位偵測器鎖相迴路時域分析 28
4 第四章 電路設計與實現 33
4.1 簡介 33
4.2 二元相位偵測器 34
4.2.1 二元相位偵測器電路設計 34
4.2.2 二元相位偵測器模擬結果 35
4.3 數位濾波器 38
4.3.1 數位濾波器電路設計 38
4.3.2 數位濾波器模擬結果 40
4.4 數位控制震盪器 42
4.4.1 數位控制震盪器電路設計 42
4.4.2 數位控制震盪器模擬結果 50
4.5 除頻器 54
4.5.1 除頻器設計 54
4.5.2 除頻器模擬結果 55
4.6 串列器 56
4.6.1 串列器設計[18] 56
4.6.2 串列器模擬結果 60
4.7 系統迴路模擬與晶片布局 62
4.8 系統模擬結果 64
5 第五章 結論 68
5.1 總結 68
5.2 未來展望 68
5.3 參考文獻 68

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