科技進步飛快，人類對於細節的要求以及資訊的快速掌握也與日俱增，但是越高的細節也意味著龐大的資料量，這些巨量的資料將會嚴重影響獲取資料的速度，所以如何實現高速資料傳遞成為一個熱門的研究課題。
一個高速串列通訊電路(Serdes)分為接收端(RX)和發射端(TX)，其中接收端包含一個時脈資料回復電路(CDR)；發射端包含一個鎖相迴路電路(PLL)。本篇論文在研究一個操作在12GHz接收端的CDR電路，目的是使接收端能夠正確的取樣到發射端給的訊號。CDR電路相較PLL困難的點為：一般PLL電路的輸出訊號會經過除頻後再做比較，整體操作頻率(除了VCO)會與參考時鐘訊號相同；CDR整體電路基本上都是全速率在運作(也有半速率型的CDR電路，但是這邊不做討論)，所以對於子電路的帶寬(bandwidth)會有相當嚴格的要求。
本篇論文是採用類比式的CDR電路，雖然目前數位式的CDR電路相當火紅，但是經過操作頻率、模擬的精確程度以及佈局的寄生問題的權衡下我還是選擇採用類比式的作法。為了有效應付高速電路，本論文的相位偵測器是採用Bang-Bang架構的非線性相位檢測器，且使用壓流轉換器(V/I Converter)讓電流在短時間內能夠快速地切換，這個切換速率與CDR本身的追蹤抖動速率密切的相關。壓控震盪器我採用的是LC壓控震盪器，與環形壓控震盪器(Ring VCO)相比，LC壓控震盪器有更好的相位雜訊表現，但缺點為龐大的電感面積，所以在選擇架構時必須針對需求做改變。CDR電路最重要的評斷標準為抖動容忍(Jitter Tolerance)，我將會用抖動容忍角度去設計一個適合的迴路頻寬(loop bandwidth)，再做穩定度模擬。
本論文採用TSMC 65nm 1P9M製程，供應電壓為1.2V，目標為一個低自主雜訊的12GHz的全速率CDR電路。

With the rapid progress of science and technology, human's requirements for details and the rapid grasp of information are also increasing day by day. However, higher details also mean a huge amount of data, which will seriously affect the speed of data acquisition, so how to achieve high-speed data transmission has become a hot research topic.
A high-speed SerDes is divided into a RX and TX. RX includes a clock data recovery circuit (CDR). TX includes a phase-locked loop circuit (PLL). This paper is studying a CDR circuit operating at the 12GHz RX. The purpose is to enable RX to sample the signal given by the transmitter correctly. The difficulty of the CDR circuit compared with the PLL is : Generally, the output signal of the PLL circuit will be divided and then compared, and the overall operating frequency (except the VCO) will be the same as the reference clock . The overall CDR circuit is basically operating at full rate (there is also a half rate CDR circuit, but it will not be discussed here), so there will be quite strict requirements for the bandwidth of the subcircuit.
This paper uses an analog CDR circuit. Although digital CDR circuit is quite popular currently, I still decided to use the analog method because of the operating frequency, the accuracy of the simulation and the parasitic problems of the layout. In order to effectively cope with high-speed circuits, the phase detector in this paper is a Bang-Bang architecture which is a nonlinear phase detector. And the use of V/I Converter allows the current to switch quickly in a short period of time. This switching rate is closely related to the jitter tracking rate of the CDR.
I use LC voltage-controlled oscillator for the voltage-controlled oscillator. Compared with Ring VCO, LC VCO has better phase noise performance. The disadvantage is the large inductor area, so the architecture must be changed according to what you need. The most important criterion for evaluating CDR circuits is Jitter Tolerance. I will use the jitter tolerance to find a suitable loop bandwidth, then simulate the stability.
This paper is made of TSMC 65nm 1P9M with a supply voltage of 1.2V. The target is to design a 12GHz full-rate CDR circuit with low autonomous noise.

摘要 i
Abstract ii
目錄 iv
圖目錄 vii
表目錄 xi
第一章 序論 1
1.1 研究動機 1
1.2 論文編排 2
第二章 時脈資料回復電路架構介紹 3
2.1 簡介 3
2.2 類比式CDR電路 3
2.2.1 相位檢測器(Phase Detector) 4
2.2.2 壓流轉換器 V/I Converter 9
2.2.3 迴路濾波器 12
2.2.4 壓控震盪器(Voltage-Controlled Oscillator) 12
2.3 數位式CDR電路 20
2.3.1 數位濾波器 21
2.3.2 數位控制震盪器 22
2.3.3 數位CDR電路總結 23
2.4 類比與數位CDR的比較 23
第三章 CDR電路的雜訊及抖動討論 25
3.1 簡介 25
3.2 資料傳輸型態 25
3.2.1 不歸零編碼NRZ Data 25
3.3 相位雜訊介紹 27
3.4 CDR電路抖動介紹 29
3.4.1 隨機抖動(Random Jitter) 30
3.4.2 固定性抖動(Deterministic Jitter) 30
3.5 CDR抖動特性 33
3.5.1 抖動傳遞(Jitter Transfer) 33
3.5.2 抖動容忍(Jitter Tolerance) 35
第四章 LC 壓控震盪器的詳細設計流程 38
4.1 LC 壓控震盪的雜訊來源分析 38
4.1.1 參雜雜訊的LC共振腔 38
4.1.2 交叉耦合對及尾電流源造成的雜訊 39
4.2 LC震盪器子電路分析 42
4.2.1 變容器(Varactor) 42
4.2.2 數位開關電容 43
4.3 VCO設計流程 46
第五章 電路佈局細節以及模擬結果 52
5.1 Alexander相位檢測器(Alexander phase detector) 52
5.1.1 D型正反器(D Flip-Flop) 52
5.1.2 CML Buffer 54
5.1.3 XOR電路 54
5.1.4 Alexander相位檢測器模擬及佈局 55
5.2 壓流轉換器(V/I Converter)模擬與佈局 58
5.3 整體迴路的線性模型與迴路濾波器的選擇 61
5.3.1 線性扭轉(linear slewing) 61
5.3.2 取RC值 65
5.4 壓控震盪器佈局與模擬 65
5.4.1 壓控震盪器佈局要點 65
5.4.2 壓控震盪器Post_sim結果 67
5.5 Matlab 開迴路及閉迴路模擬 70
5.6 迴路模擬 72
第六章 結論 77
6.1 總結 77
6.2 未來展望與挑戰 77
參考資料 78

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