由於電晶體數目的指數增長趨勢，超大型積體電路的複雜程度不斷提高，許多微小的製程缺陷難以透過傳統的測試方法進行檢測。然而這些微小的缺陷可能會降低晶片產品的品質與可靠性。在本論文中，基於一個以憶阻器建構的脈衝神經網路架構，我們的實驗展示了在高密度電阻式記憶體單元陣列中的微小硬體缺陷，可能導致晶片的計算準確度下降，也可能因為功率消耗上升，在晶片內部產生額外的熱源。為了提升晶片的可靠度，我們提出運用群體熱感知及共生系統架構以提升基於憶阻器的脈衝神經網路硬體的可靠度。我們也提出了一個低功耗與低成本的溫度感測器電路架構，可以被大量部署於群體熱感知系統中，以偵測晶片中的熱源分布佈情形。我們也提出了共生系統架構，透過一個次系統脈衝神經網路，我們對熱源分佈情形進行監控，以推論主系統脈衝神經網路中是否存在錯誤。實驗結果顯示，次系統脈衝神經網路進行偵錯的準確度可達到91.6%，整個群體熱感知及共生系統僅增加2.48%晶片面積。當有錯誤被偵測到時，藉由調整脈衝神經網路中神經元的閾值電壓進行補償，我們可以減緩晶片計算結果的準確度下降趨勢，進而提升晶片的可靠度。

Due to the exponential growth of transistor density and complexity of VLSI circuits, it is increasingly challenging to detect the subtle defects in VLSI circuits by traditional testing methods. These hard-to-detect defects, however, may degrade the product’s reliability and quality. In this paper, based on a memristor-based spiking neural network (SNN) architecture that we have designed, we show that the subtle defects in the compact memristor cell array and the SNN functional faults may result in inference accuracy loss and extra heat generated by the SNN chip. To achieve a reliable memristor-based SNN chip, we propose an on-chip thermal quorum sensing scheme that can monitor the temperature distribution on the chip. We also propose the symbiotic neuromorphic architecture, where a secondary-SNN is developed for on-line real-time failure detection for the primarySNN. Simulation results show that the secondary-SNN achieves 91.6% detection accuracy, with only 2.48% silicon area overhead. When a failure is detected, our compensation scheme can recover the inference accuracy loss of the SNN chip.

Abstract (Chinese) . . . . . . . . . . . . . . . . . . . . . . . I
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . II
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . III
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . V
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . VIII
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Proposed Method and Results . . . . . . . . . . . . . . . . . 2
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . 3
2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Introduction to Symbiotic System . . . . . . . . . . . . . . 4
2.2 Introduction to Thermal Quorum Sensing . . . . . . . . . . . 5
2.2.1 Quorum Sensing . . . . . . . . . . . . . . . . . . . . . . 5
2.2.2 Introduction to Thermal Quorum Sensing . . . . . . . . . . 5
2.3 Introduction to Spiking Neural Network . . . . . . . . . . . 6
2.4 Introduction to Memristor-Based SNN . . . . . . . . . . . . . 7
2.4.1 Memristor . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4.2 1T1R Memristor Structure . . . . . . . . . . . . . . . . . 8
2.4.3 Memristor-Based SNN Chip . . . . . . . . . . . . . . . . . 9
3 Proposed Thermal Sensor Circuit . . . . . . . . . . . . . . . . 14
3.1 Circuit Schematic and Layout . . . . . . . . . . . . . . . . 15
3.2 Sensor Design Concept . . . . . . . . . . . . . . . . . . . . 16
3.3 Circuit Calibration Methodology . . . . . . . . . . . . . . . 20
4 Online Monitoring System . . . . . . . . . . . . . . . . . . . 24
4.1 Memristor Power Model . . . . . . . . . . . . . . . . . . . . 24
4.2 Memristor-Based SNN Faulty Behavior . . . . . . . . . . . . . 26
4.3 Thermal Quorum Sensing Scheme . . . . . . . . . . . . . . . . 28
4.3.1 Thermal Quorum Sensing Scheme . . . . . . . . . . . . . . . 28
4.3.2 Secondary Neural Network . . . . . . . . . . . . . . . . . 29
4.4 Compensation Technique . . . . . . . . . . . . . . . . . . . 30
5 Experimental Results . . . . . . . . . . . . . . . . . . . . . 32
5.1 Fault-Free Power & Temperature . . . . . . . . . . . . . . . 33
5.2 Faulty Power & Temperature . . . . . . . . . . . . . . . . . 34
5.3 Secondary Neural Network Testing Result . . . . . . . . . . . 36
5.4 Area Overhead . . . . . . . . . . . . . . . . . . . . . . . . 37
5.5 Compensation Results . . . . . . . . . . . . . . . . . . . . 37
6 Conclusion and Future Work . . . . . . . . . . . . . . . . . . 39
6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . 40
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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