突波神經網路(Spiking neural networks, SNNs)作為第三代人工神經網路模型，相較於傳統的類神經網路(Artificial neural networks, ANNs)更接近生物神經元的運作方式， 突波神經網路透過二進位值輸入和輸出突波進行訊息傳遞，模擬神經元在時間和空間中的突波傳遞模式，因為僅記載突波發生與否，特別適合處理複雜的時空數據，在邊緣硬體上可節省大量運算能耗。神經形態運算被視為機器學習的未來，提供了一種新的認知計算方式，對於突波神經網路模擬的硬體加速器的需求正在迅速增加。
突波神經網路先天的高稀疏性以及事件驅動運算特性帶來的低功耗適合對能耗要求極高的邊緣裝置。此外，在資源受限移動式裝置上，我們同時要求少的儲存空間需求。突波神經網路與傳統的人工神經網路相比，非常適合處理複雜與具有時間維度相關性的資料，然而，常見的突波神經網路晶片針對不同時間步的計算是採取重複訪問資料的方式，導致高能耗。
本研究提出一跨時間步並行計算以及高效突觸記憶體結構之硬體加速架構，並具備激發神經元權重搜索電路的突波稀疏感知策略，以此達到更低的能耗、更少的硬體資源使用量、更高能效膜電位累加計算等優勢。此論文提出之架構與方法應用於完全連接的 256-128-128-10 網絡，對 16×16 MNIST 訓練圖像進行分類，達到 0.2 pJ/SOP 的能量效率，最高1.9倍的加速以及減少2倍的記憶體存取次數。

Spiking Neural Networks (SNNs), as the third generation of artificial neural network models, are closer to the operation mode of biological neurons compared to traditional Artificial Neural Networks (ANNs). SNNs transmit information through binary value input and output spikes, simulating the spiking transmission patterns of neurons in time and space. Because only the occurrence of spikes is recorded, they are particularly suitable for processing complex spatiotemporal data and can save a significant amount of computational energy on edge hardware. There is a rapidly increasing demand for hardware accelerators simulating SNNs. The inherent high sparsity and low power consumption characteristics of SNNs, due to event-driven computation, make them suitable for edge devices with extremely high energy consumption requirements. Furthermore, in resource-constrained mobile devices, we also require minimal storage space. Compared to traditional ANNs, SNNs are very suitable for processing complex data with temporal correlations. However, common spiking neural network chips typically involve repeated data access for computations at different time steps, leading to high energy consumption.
This study proposes a hardware acceleration architecture with Temporally Parallel Weight-Friendly (TPWF) dataflow and efficient synaptic memory structures. It also incorporates a spiking sparse sensing strategy for excitatory neuron weight searching circuits to achieve lower energy consumption, reduced hardware resource usage, and higher energy-efficient membrane potential accumulation calculations. The proposed architecture and methods are applied to a fully connected 256-128-128-10 network for classifying 16×16 MNIST training images, achieving an energy efficiency of 0.2 pJ/SOP, up to 1.9 times acceleration, and reducing memory access times by 2 times.

摘要............I
ABSTRACT........II
目錄............III
圖目錄.......... V
表格目錄........ VII
第 1 章 緒論.................1
1.1 研究背景.............1
1.2 研究動機與目的........4
1.3 章節簡介..............7
第 2 章 文獻回顧..............8
2.1 突波神經網路架構.......8
2.1.1 神經元模型.............8
2.1.2 突波神經網路架構...........9
2.1.3 時間順序處理資料流.........10
2.1.4 資料復用..................10
2.1.5 輸入稀疏性................11
2.1.6 權重稀疏性................13
2.2 突波神經網路加速器.........14
2.2.1 時間順序處理資料流之加速器..14
2.2.2 資料復用..................15
2.2.3 片上記憶體空間壓縮.........16
2.3 研究動機.................17
第 3 章 具時間平行數據流與高效記憶體壓縮的突波神經網路加速器.....19
3.1 突波神經網路加速器架構.....19
3.2 突波運算行為與數據流...... 25
3.2.1 神經元模型與電路(I-QIF neuron model)......25
3.2.2 時間並行數據流(Temporally Parallel Weight-Friendly dataflow) 26
3.2.3 後突觸系統架構(Post-synaptic core design)..29
3.3 基於脈動陣列的輸入稀疏感知與權重映射.........32
3.3.1 輸入稀疏性跳零機制(Input Sparsity Zero-Skipping mechanism)32
3.3.2 隨機突波與權重映射 (Random Spiks and Weight Mapping)......34
3.4 權重壓縮機制架構與權重搜索..36
3.4.1 長度壓縮編碼與定義(Run Length Encoding Definition) 36
3.4.2 突觸權重映射 (Sparse Synaptic Weight Mapping).....38
3.4.3 記憶體索引編碼(Sparsity Index Code)...............38
3.4.4 激發神經元權重搜索 (Burst Neuron Weight Search Mechanism).40
第 4 章 實驗結果...................42
4.1 FPGA 系統驗證與環境設置.....42
4.2 加速器效能分析與神經網路應用.44
4.2.1 加速幅度分析..........44
4.2.2 記憶體存取次數分析.....45
4.2.3 稀疏化感知架構成效.....46
4.3 與先進加速器效能比較...49
第 5 章 結論與未來發展........51
參考文獻.....................53

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