近年來無線通訊技術發展快速，視訊直播、雲端運算、物聯網等大量和通訊相關之產業，帶起了對於頻寬的需求，現在人們越來越依賴串流影音平台，當作是一種消遣娛樂，不再滿足於現在的畫質和傳輸速度，未來傳輸速度的提升，將成為科技發展重要的一環。
本論文實現一個類比式鎖相迴路，使用台積電65nm的製程設計，電路組成包含相位頻率檢測器、充電汞、低通濾波器、電壓控制震盪器和除頻器。相位頻率檢測器內的TSPC-D型正反器透過MOSFET工作區分析，可將電路簡化，不但能達到減少電晶體使用之目的而且能得接近方波之暫態響應，讓頻率檢測器在比較時能更加精確，於壓控震盪器使用交叉耦合的設計來達到需要的震盪頻率，最後透過整數除頻器構成完整的類比式鎖相迴路架構。
論文開頭介紹各種鎖相迴路基本架構並進行比較，接著依序講解類比式鎖相迴路之數學模型、設計流程及個子電路的模擬結果，最後再對本論文提出的鎖相迴路架構做簡單的結論。

In recent years, wireless communication technology has developed rapidly. Many communication-related industries such as live video broadcast, cloud computing, and IoT have brought about the demand for bandwidth. Nowadays, people are no longer satisfied with the current picture quality and transmission speed, and the improvement of transmission speed in the future will become an important part of the development of science and technology.
This paper implements an phase-locked loop with TSMC's 65nm process design. The circuit consists of a phase frequency detector, charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider. The TSPC-D type flip-flop in the phase frequency detector which can not only achieve the purpose of reducing the use of transistors, but also allowing the frequency detector can be more accurate. The cross-coupling design is used in the voltage-controlled oscillator to achieve the required frequency. Finally, a complete phase-locked loop structure is formed through an integer frequency divider.
At the beginning of the paper, the basic structures of various PLLs are introduced and compared, and then the mathematical model, design process and simulation results of each sub-circuit of the analog PLL are explained in sequence. Finally, a simple conclusion is made on the PLL structure proposed in this paper.

摘要 I
Abstract II
目錄 III
圖目錄 V
表目錄 VII
第一章 序論 1
1.1 研究動機 1
1.2 章節介紹 1
第二章 鎖相迴路架構及基本原理介紹 2
2.1 鎖相迴路種類介紹 2
2.1.1 類比式鎖相迴路 2
2.1.2 數位式鎖相迴路 3
2.1.3 全數位式鎖相迴路 3
2.2 數位式鎖相迴路介紹 4
2.2.1 相位頻率檢測器 4
2.2.2 電流幫浦 7
2.2.3 迴路濾波器 9
2.2.4 壓控震盪器 11
2.2.5 除頻器 16
2.3 全數位式鎖相迴路介紹 18
2.3.1電路架構及操作 18
2.3.2時間數位轉換器 18
2.3.3 數位迴路濾波器 22
2.3.4 數位壓控震盪 24
2.4 鎖相迴路架構比較 25
第三章 鎖相迴路電路實現及雜訊分析 27
3.1相位頻率檢測器 27
3.2 電流幫浦 30
3.3 迴路濾波器 31
3.4 電壓控制震盪器 32
3.5 除頻器 34
3.6 鎖相迴路雜訊分析 35
第四章 模擬結果 40
4.1相位頻率檢測器 40
4.2電流幫浦 43
4.3壓控震盪器 45
4.4除頻器 46
4.5迴路模擬 47
第五章 結論 48
參考文獻 49

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