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作者(中文):趙德昊
作者(外文):Zhao, De-Hao
論文名稱(中文):硬體加速之模組化演算法交易系統
論文名稱(外文):A Hardware-Accelerated Modular Algorithmic Trading System
指導教授(中文):馬席彬
指導教授(外文):Ma, Hsi-Pin
口試委員(中文):黃稚存
黃元豪
楊家驤
口試委員(外文):Huang, Chih-Tsun
Huang, Yuan-Hao
Yang, Chia-Hsiang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學號:109061603
出版年(民國):111
畢業學年度:111
語文別:中文
論文頁數:56
中文關鍵詞:硬體加速場效可程式化邏輯閘陣列交易系統交易策略期貨選擇權
外文關鍵詞:Hardware AccelerationFPGATrading SystemTrading StrategyFuturesOptions
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使用程式做為交易方法的交易商在現代金融市場日益增加,目前已有許多人使用硬體描述性語言以及場域可程式化邏輯閘陣列實現硬體加速的交易系統,針對特定的金融協議或是交易所進行最佳化,雖然達到了低延遲的效果,卻可能因為過度最佳化或是系統功能模組相依性過高,使得交易系統在變化快速的金融市場失去了靈活性。

本篇論文提出一個模組化的演算法交易系統,我將交易系統分成網路層、協議層與策略層,並且定義各層模組與模組之間的傳輸介面,使開發者能夠迅速地完成硬體系統的開發、驗證與部屬,當交易所定義的金融協議或是系統需求變動時,也可以有效率地對系統進行調整。另外,我與合作廠商皓德盛科技有限公司共同開發新的期權定價方法,能夠在 112.5 ns 內計算出選擇權價格,與市場價格誤差小於 0.35%,最後以台灣期貨交易所為例,在 Xilinx® Alveo™ U50 Data Center Accelerator Cards FPGA 板上實現了一個完整的交易系統,該系統在兼具靈活性的同時達到了 637 ns的延遲。
The number of traders who use programs as a trading method is increasing in the modern financial market. At present, many people use hardware description language (HDL) and field-programmable gate array (FPGA) to implement hardware-accelerated trading systems, which are optimized for specific financial protocols or exchanges. Although it achieves the effect of low latency, it may be due to over-optimization or high interdependence of system function modules, which makes the trading system lose flexibility in the fast-changing financial market.

This paper proposes a modular algorithmic trading system. I divide the trading system into network layer, protocol layer and strategy layer, and define the transmission interface between modules and modules at each layer.
This enables developers to quickly complete the development, verification and deployment of the hardware system, and can efficiently adjust the system when the financial protocol defined by the exchange or the system requirements change.
In addition, I jointly developed a new option pricing method with the partner company Vsense Fintech Inc., which can calculate the option price within 112.5 ns, and the error between the calculation result and the market price is less than 0.35%.
Finally, I took the Taiwan Futures Exchange as an example, and implemented a complete trading system on the Xilinx® Alveo™ U50 Data Center Accelerator Cards FPGA board to achieve 637 ns latency and high flexibility.
誌謝. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
第一章緒論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 研究背景. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 研究動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 主要貢獻. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 論文大綱. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
第二章文獻回顧. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 交易系統相關文獻. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 交易系統架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.2 交易系統加速設計. . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 文獻分析. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
第三章架構設計. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 系統概述. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 饋送處理器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 委託簿. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 自定義策略. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 訂單輸入. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 直接記憶體存取模組. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.7 策略介紹. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.7.1 演算法. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7.2 改良式二元搜尋. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.7.3 市場參數計算. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
第四章實作與結果驗證. . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1 驗證方法. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.1 策略演算法. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.2 交易系統. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2 硬體使用率. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3 結果驗證與比較. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3.1 改良式二元搜尋. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3.2 期權定價方法. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3.3 系統效能評比. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
第五章結論與未來規劃. . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1 結論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.2 未來規劃. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
參考文獻. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
[1] J. Brogaard et al., “High frequency trading and its impact on market quality,” Northwestern
University Kellogg School of Management Working Paper, vol. 66, 2010.
[2] A. Gerig, “High frequency trading synchronizes prices in financial markets,” arXiv.org,
Papers, Nov. 2012. [Online]. Available: https://ideas.repec.org/p/arx/papers/1211.1919.
html
[3] C. Leber, B. Geib, and H. Litz, “High frequency trading acceleration using FPGAs,” in
2011 21st International Conference on Field Programmable Logic and Applications, 2011,
pp. 317–322.
[4] Q. Tang, M. Su, L. Jiang, J. Yang, and X. Bai, “A scalable architecture for low-latency
market-data processing on FPGA,” in 2016 IEEE Symposium on Computers and Communication
(ISCC), 2016, pp. 597–603.
[5] J. W. Lockwood, A. Gupte, N. Mehta, M. Blott, T. English, and K. Vissers, “A lowlatency
library in FPGA hardware for high-frequency trading,” in 2012 IEEE 20th Annual
Symposium on High-Performance Interconnects, 2012, pp. 9–16.
[6] A. Boutros, B. Grady, M. Abbas, and P. Chow, “Build fast, trade fast: FPGA-based highfrequency
trading using high-level synthesis,” in 2017 International Conference on Re-
ConFigurable Computing and FPGAs (ReConFig), 2017, pp. 1–6.
[7] H. R. Stoll, “The relationship between put and call option prices,” The Journal
of Finance, vol. 24, no. 5, pp. 801–824, 1969. [Online]. Available: https:
//onlinelibrary.wiley.com/doi/abs/10.1111/j.1540-6261.1969.tb01694.x
[8] N. Chriss and N. Chriss, Black Scholes and Beyond: Option Pricing Models. McGraw-
Hill Companies,Incorporated, 1997. [Online]. Available: https://books.google.com.tw/
books?id=8q9v1ZekHEEC
[9] S. Min, M. Alian, W.-M. Hwu, and N. S. Kim, “Semi-Coherent DMA: An alternative
I/O coherency management for embedded systems,” IEEE Computer Architecture Letters,
vol. 17, no. 2, pp. 221–224, 2018.
[10] W. wu and M. Crawford, “Potential performance bottleneck in Linux TCP,” Int. J. Communication
Systems, vol. 20, pp. 1263–1283, 11 2007.
[11] FAST Specification Version 1.1. FIXTrading Community, 2017.
[12] D. Slogsnat, A. Giese, M. Nüssle, and U. Brüning, “An open-source HyperTransport
core,” ACM Transactions on Reconfigurable Technology and Systems, vol. 1, no. 14,
pp. 1–21, 2008.
[13] R. Pottathuparambil, J. Coyne, J. Allred, W. Lynch, and V. Natoli, “Low-latency FPGA
based financial data feed handler,” in 2011 IEEE 19th Annual International Symposium
on Field-Programmable Custom Computing Machines, 2011, pp. 93–96.
[14] M. Dvořák and J. Kořenek, “Low latency book handling in FPGA for high frequency trading,”
in 17th International Symposium on Design and Diagnostics of Electronic Circuits
Systems, 2014, pp. 175–178.
[15] R. Pagh and F. F. Rodler, “Cuckoo hashing,” J. Algorithms, vol. 51, no. 2, p. 122–144,
may 2004. [Online]. Available: https://doi.org/10.1016/j.jalgor.2003.12.002
[16] H. Kan, R. Hao, J. Wang, G. Mei, D. Su, and S. Deng, “HLS based ultra-low latency FAST
protocol decoder,” ser. CSAE 2021. New York, NY, USA: Association for Computing
Machinery, 2021. [Online]. Available: https://doi.org/10.1145/3487075.3487150
[17] R. Nageshwara and V. Kumar, “Concurrent access of priority queues,” IEEE Transactions
on Computers, vol. 37, no. 12, pp. 1657–1665, 1988.
[18] Y.-C. Kao, H.-A. Chen, and H.-P. Ma, “An FPGA-based high-frequency trading system
for 10 gigabit ethernet with a latency of 433 ns,” in 2022 International Symposium on
VLSI Design, Automation and Test (VLSI-DAT), 2022, pp. 1–4.
[19] Tick-by-tick Market Information Transmission Operation Manual. Taiwan Futures Exchange,
2020.
[20] Taiwan Futures Market TCP/IP TMP Messaging Specifications. Taiwan Futures Exchange,
2022.
[21] F. Black and M. Scholes, “The pricing of options and corporate liabilities,” Journal of
political economy, vol. 81, no. 3, p. 637, 1973.
[22] G. Chatziparaskevas, A. Brokalakis, and I. Papaefstathiou, “An FPGA-based parallel processor
for Black-Scholes option pricing using finite differences schemes,” in 2012 Design,
Automation Test in Europe Conference Exhibition (DATE), 2012, pp. 709–714.
[23] I. Stamoulias, C. Kachris, and D. Soudris, “Hardware accelerators for financial applications
in HDL and high level synthesis,” in 2017 International Conference on Embedded
Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2017, pp. 278–
285.
 
 
 
 
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