這篇論文提出一顆十三位元低過取樣速率五階雜訊塑形連續漸進式(successive-approximation register, SAR)類比數位轉換器(analog-to-digital converter, ADC)。
關鍵的雜訊塑形過濾器(noise shaping filter)部分使用了改良過的電壓-時間-電壓(Voltage-Time-Voltage, V-T-V)轉換器提供了可靠的開環增益,由於此增益主要來自於兩顆不同電容與兩條不同電流之間的比例,其增益本質上對於製程、電壓與溫度(Process-Voltage-Temperature, PVT)具有不敏感性,因此並不需要額外的校正或修剪即可實現理想的雜訊轉換函數 (noise transfer function, NTF)。此外,V-T-V轉換器只消耗動態功率。透過使用元件比例設計與動態功耗方式,所提出的ADC具有抵抗PVT變異與良好功率效益的特性。本作更解決了原本電流雜訊的問題，將ADC的解析度上升到更高的位置。
為了驗證本電路,此架構使用40奈米1P10M互補式金氧半導體製程製作,核心電路面積為 590 x 100um2,在1.1伏特電源電壓及五百萬赫茲取樣頻率操作下,此晶片在625千赫茲輸入頻寬實現之SNDR為81.8dB,其對應的ENOB為13-bit,功率消耗為90微瓦,而等效的Walden figure of merit (FoMW)為7.2fJ/conversion-step,Schreier figureof merit (FoMS)為180.2dB。

This paper presents a 13-bit low oversampling rate 5th-order noise-shaping successive-approximation register (SAR) analog-to-digital converter (ADC). The key component of the noise-shaping filter utilizes a reliable open-loop gain Voltage-Time-Voltage (V-T-V) converter. The gain primarily stems from the ratio of two different capacitors and two distinct currents, making it inherently insensitive to Process-Voltage-Temperature (PVT) variations. As a result, no additional calibration or trimming is required to achieve the desired noise transfer function (NTF). Furthermore, the V-T-V converter operates with dynamic power consumption. By employing component ratio design and dynamic power approach, the proposed ADC exhibits resistance to PVT variations and excellent power efficiency. This work further addresses the issue of current noise, elevating the resolution of the ADC to a higher level.
To validate this circuit, the architecture was fabricated using a 40nm 1P10M CMOS process. The core circuit area is 590 x 100um2. Operating at a supply voltage of 1.1V and a sampling frequency of 5MHz, this chip achieves an SNDR of 81.8 dB with a 625 kHz input bandwidth. The ENOB is 13 bits, and the power consumption is 90uW. The equivalent Walden figure of merit (FoMW) is 7.2 fJ/conversion-step, and the Schreier figure of merit (FoMS) is 180.2 dB.

Key words : noise-shaping SAR, V-T-V converter, low OSR, 5th-order NTF, PVT insensitive

ABSTRACT I
CONTENTS IV
LIST OF FIGURES VIII
LIST OF TABLES XI
CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 SELECTION OF ARCHITECTURE 1
1.3 THESIS ORGANIZATION 3
CHAPTER 2 FUNDAMENTALS OF ADC 4
2.1 NYQUIST THEOREM 4
2.2 RESOLUTION 5
2.3 OFFSET ERROR 5
2.4 GAIN ERROR 6
2.5 QUANTIZATION ERROR 7
2.6 SIGNAL-TO-NOISE RATIO (SNR) AND EFFECTIVE NUMBER OF BITS (ENOB) 9
2.7 SIGNAL-TO-NOISE AND DISTORTION RATIO (SNDR) 10
2.8 EFFECTIVE NUMBER OF BITS (ENOB) 10
2.9 DIFFERENTIAL NONLINEARITY (DNL) 11
2.10 INTEGRAL NONLINEARITY (INL) 12
2.11 SPURIOUS-FREE DYNAMIC RANGE (SFDR) 13
2.12 FIGURE OF MERIT (FOM) 13
CHAPTER 3 OVERVIEW OF ADCS 14
3.1 TOP-LEVEL DISCUSSIONS 14
3.1.1 SAR ADC 14
3.1.2 Sigma-Delta Modulator (DSM or SDM) 16
3.1.3 Noise Shaping SAR ADC 18
3.2 SAMPLE AND HOLD (S/H) CIRCUITS 20
3.2.1 Sampling Speed 20
3.2.2 Signal Dependent Resistance 21
3.2.3 Charge Injection 22
3.2.4 Clock Feedthrough 23
3.2.5 kT/C Noise ……………………………………………………………. .24
3.3 DIGITAL-TO-ANALOG CONVERTER USING CAPACITIVE ARRAY 25
3.3.1 Parasitic Capacitance 26
3.3.2 Mismatch 27
3.4 COMPARATOR 28
3.4.1 Input-referred offset 29
3.5 ASYNCHRONOUS SAR LOGIC 30
3.6 STRUCTURE OF NOISE SHAPING SAR ADC 31
3.6.1 Cascaded Integrator Feed-Forward 31
3.6.2 Error-Feedback 32
3.7 SUMMARY 33
CHAPTER 4 DESIGN CONSIDERATIONS OF NOISE SHAPING SAR ADC 35
4.1 DIFFERENTIAL ADC 36
4.2 SAMPLE AND HOLD 37
4.3 COMPARATOR 37
4.4 CDAC 38
4.5 IMPLEMENTATION OF RESIDUE PROCESS 40
4.5.1 Prior Art 40
4.5.2 Signal Model 43
4.5.3 Non-Ideal Effect 44
4.6 SUMMARY 46
CHAPTER 5 CIRCUIT IMPLEMENTATION OF PROPOSED NOISE SHAPING SAR ADC 47
5.1 ARCHITECRURE OF PROPOSED NS SAR ADC 48
5.2 ARCHITECRURE OF PROPOSED V-T-V CONVERTER 50
5.3 DESIGN OF V-T-V CONVERTER AND SC FIR FILTERS 53
5.4 DESIGN OF SAMPLE AND HOLD (S/H) 54
5.5 DESIGN OF COMPARATOR 55
5.6 DESIGN OF CAPACITIVE DAC (C-DAC) 57
5.7 PRE-LAYOUT AND POST-LAYOUT SIMULATION 59
5.8 SUMMARY 61
CHAPTER 6 EXPERIMENTAL RESULTS 63
6.1 MEASUREMENT ENVIRONMENT SETUP 63
6.2 CHIP MICROGRAPH 64
6.3 MEASUREMENT RESULTS 65
6.4 PERFORMANCE COMPARISON 68
6.5 SUMMARY 68
CHAPTER 7 CONCLUSION 70
7.1 CONCLUSION 70
7.2 FUTURE WORK 70
BIBLIOGRAPHY 72

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