全數位式鎖相迴路相較於類比式鎖相迴路，在面積與功耗上有著更好的優勢，而其全數位式的架構，也更利於隨著先進製程進行演進與轉移。本論文提出一具有製程適應能力且振盪頻率為6.4-GHz之全數位式鎖相迴路，主要組成電路有一位元式相位偵測器、數位濾波器、二進制碼轉溫度計碼解碼器、數位控制振盪器、與多模數除頻器。
相位偵測的部分使用一位元式相位偵測器，並修改電路架構，改善速度不平衡之問題。數位濾波器之電路設計採用上下數計數器之架構來取代類比式之迴路濾波器，並加入掃描鏈電路以大幅減少迴路鎖定所需之時間。加入二進制碼轉溫度計碼解碼器來減緩變換切換式電容組時，對鎖相迴路輸出頻率造成之毛刺現象。數位控制振盪器架構上採用LC共振槽架構，並以變換全切換式電容組之方式達到調變振盪頻率之功能，其過程皆直接由數位碼進行控制，省去數位類比轉換器電路之使用。並對切換式電容組之組數與大小進行設計與調整，使鎖相迴路具有對抗製程工藝角之能力。透過以上子電路建構出完整的全數位式鎖相迴路電路。
本論文採用台積電65奈米製程技術進行實體電路架構分析與模擬佈局，論文開頭先進行各架構鎖相迴路之簡介與比較，接著對全數位式鎖相迴路中各子電路進行分析、設計、佈局、與其模擬結果之呈現，最後再對論文所提出之鎖相迴路進行統合性的結論。

Compare with the analog phase-locked loops (APLL), the all-digital phase-locked loops (ADPLL) have better advantages in area and power consumption, and its all-digital architecture is also more conducive to the evolution and transfer with the advanced process. We propose a 6.4-GHz Integer-N All-Digital Phase-Locked Loop with Process Variation Tolerance in this thesis, it consists of a bang-bang phase detector (BBPD), a digital loop filter (DLF), a binary-to-thermometer decoder (B2T), a digital-controlled oscillator (DCO), and a multi-modulus frequency divider.
The part of the phase detection adopts a bang-bang phase detector, and the circuit structure is modified to improve the problem of speed imbalance. The circuit design of the digital loop filter adopts the circuit structure of the up-down counter to replace the analog loop filter, and adds a scan chain circuit to greatly reduce the time required for loop locking. A binary-to-thermometer decoder is added to reduce the frequency glitches caused by the conversion of switched capacitor bank. The LC resonant tank structure is used in the digital-controlled oscillator, and the function of modulating the oscillation frequency is achieved by changing the status of switched capacitor bank. The process is directly controlled by the digital code, eliminating the need for a digital-to-analog converter circuit (DAC). Design and adjust the number and size of switched capacitor bank, so that the phase-locked loop has the ability to resist the variation of process corner. Through the above sub-circuits, the entire architecture of ADPLL circuit is constructed.
This thesis is implemented by TSMC 65nm process. In the beginning, the introduction and comparison with different architecture of PLL are carried out, and then present the analysis, design, layout, and simulation of each sub-circuits of the ADPLL, and finally, make a conclusion for the ADPLL proposed in this thesis.

摘要 i
Abstract ii
目錄 iii
圖目錄 v
表目錄 ix
第一章 緒論 1
1.1 研究動機 1
1.2 論文章節介紹 2
第二章 各鎖相迴路架構之說明 3
2.1 簡介 3
2.2 類比式鎖相迴路 3
2.3 全數位式鎖相迴路 6
2.4 鎖相迴路架構之比較 10
第三章 電路設計與實現 11
3.1 簡介 11
3.2 一位元式相位偵測器電路設計 12
3.3 數位濾波器電路設計 17
3.4 二進制碼轉溫度計碼解碼器電路設計 23
3.5 數位控制振盪器電路設計 28
3.5.1 電感電容式振盪器電路設計 29
3.5.2 電流源電路設計 32
3.5.3 切換式電容電路設計 36
3.6 多模數除頻器電路設計 41
第四章 佈局規劃與模擬結果 46
4.1 一位元式相位偵測器佈局與模擬結果 46
4.2 數位濾波器佈局與模擬結果 48
4.3 二進制碼轉溫度計碼解碼器佈局與模擬結果 51
4.4 數位控制振盪器佈局與模擬結果 56
4.5 多模數除頻器佈局與模擬結果 62
4.6 全數位式鎖相迴路模擬結果 65
第五章 結論 69
參考文獻 70

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