2017年數字系統POSIT [1]被提出，與傳統浮點數IEEE754相比，相同的位元下，可提供更大的動態範圍和更多的小數位以提高準確性，其在接近 1 的範圍具有特別好的精度。Posit數字系統在當前應用中，較常用於深度學習，因其研究趨勢中試圖最大限度減少使用位元數，並得到類似的結果。通過使用更少的位元來實現加速，從而減少網絡和內存帶寬以及功率要求。
然對於其精度的應用探討則較少討論到，本論文主旨在提供一個新方法—使用固定點迭代法以計算Posit數字系統的平方根，並和其他浮點數字系統比較，包含雙精度浮點、單精度浮點、半精度浮點、和bfloat16。本論文首先說明各數字系統，並比較現行的硬體演算法中Posit格式的運算單元，其次說明使用固定點迭代法求平方根的演算法，以及其硬體架構，最後將此演算法實現在FPGA上，並設計一套UI介面以輔助驗證收斂速度和精度，得出其延遲、面積與功耗，在初始值為1的版本中，Posit(16,1)、Posit(32,1)和Posit(32,2)的LUT分別為375、1000和985，其面積在Posit(16,1)優於 [2]的386；面積在Posit(32,2)優於 [3]的1084(iterative)和2121(pipeline)；面積在Posit(32,1)則介於 [3]的1088(iterative)和2131(pipeline)和 [2]的832之間，而在加入初始值控制的單元後，Posit(16,1)和Posit(32,2)的LUT分別為379和1001，但得到迭代次數下降的運算效益。

In 2017, the number system POSIT was proposed. Compared with the traditional floating point number system IEEE754, it can provide a larger dynamic range and more decimal places to improve the accuracy under the same number of bits. It has a particularly good performance in the range close to 1. Recently deep learning trends try to minimize the number of bits and get similar results. By using fewer bits to reduce network and memory bandwidth and power requirements.
However, the application of its precision is less discussed. The main purpose of this article is to use the fixed-point iteration method to calculate the square root in the posit number system, and compare it with the traditional floating-point IEEE754. This paper first describes each digital system, and compares the arithmetic units of the Posit format in the current hardware algorithm. Secondly, it describes the algorithm for finding the square root using the fixed-point iterative method and its hardware architecture. Finally, the algorithm is implemented in an FPGA and design a set of UI interface to help verify the convergence speed and accuracy, and obtain its delay, area and power consumption. In the version with the initial value of 1, the square root calculator in Posit(16,1),Posit(32,1),Posit(32,2) is 375, 1000 and 985, its area in Posit(16,1) is better than 386 in [2]; the area in Posit(32,2) is better than 1084 (iterative) and 2121 (pipeline) in [3]; the area is in Posit(32,1) is between 1088 (iterative) and 2131 (pipeline) of [3] and 832 of [2]. In the version with the initial value control unit, the square root calculator in Posit(16,1) and Posit(32,2) is 379 and 1001, which get the computational benefit of reducing the number of iterations.

中文摘要 I
Abstract II
誌謝 III
目錄 IV
圖目錄 VI
表目錄 X
第一章 緒論 1
1.1 研究背景與目標 1
1.2 文獻回顧 1
1.3 論文架構 5
第二章 研究背景與相關研究 6
2.1 數字系統 6
2.1.1 IEEE754 6
2.1.2 半精度浮點 6
2.1.3 bfloat16 7
2.1.4 Posit [1] 8
2.2 硬體運算單元 10
2.2.1 PACoGen [4] 10
2.2.2 Flo-Posit [5] 23
2.2.3 PLAM [6] 23
2.3 固定點迭代法 26
2.3.1 固定點 26
2.3.2 迭代式 26
2.3.3 巴拿赫固定點定理逆定理證明 27
第三章 分析方法與實驗結果 28
3.1 基礎運算單元 28
3.2 平方根求解 44
3.2.1 平方根迭代函數 44
3.2.2 平方根硬體架構 45
3.3 UI介面轉換器 55
3.4 實驗結果 61
3.4.1 數值驗證 61
3.4.2 加入初始值控制之迭代驗證 73
第四章 結論與未來展望 79
4.1 結論 79
4.2 未來展望 79
參考文獻 80

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