由於現今電子裝置的製作重心在於更輕薄、體積小，一種無核芯(coreless)的基版技術被研發及發展、稱為嵌入式基板(Embedded Trace Substrate, ETS)，並廣泛應用於各式電子產品，如:通訊用具、智慧型手錶以及各式各樣消費型產品。然而，此種設計因為不同材料間的相異的物理性質而有嚴重的缺陷，舉例而言，在回焊製程中，因銅線與與其他非金屬材料的熱膨脹係數(Coefficient of thermal expansion, CTE)不匹配，會造成產品發生嚴重的翹曲(warpage)，進而影響後續封裝製程(package processing)。近年來，有限元素分析法(Finite Element Analysis, FEA)是一種受歡迎且有效的方法幫助研究人員預測板彎翹曲和機械性質的研究。生產者可以應用有限元素方法去模擬基板的改良設計，以及能提供一個特定的翹曲數值滿足後續開發所需。儘管如此，對於高精度的模擬需耗費龐大的計算成本，因此，如果必須多次執行模擬研究（如靈敏度分析和翹曲優化），則模擬研究將成為漫長而艱鉅的任務。
在此篇論文中，提出三種等效方法來降低有限元素法的分析效率與難度，並透過COMSOL及ANSYS二種軟體設計出三種不同的案例預測板彎翹曲，找出最佳的設計方法。有別於傳統的try and error或是實驗設計法(DOE)，需要透過大量實驗來得到較佳的翹曲結果，本文提出的方法結果顯示與實際實驗相符且精準。若將來將此方法運用於工業上，使得在封裝製程的預處理步驟中，能直接藉由參數的調整進行板彎翹曲的優化，提升檢測和設計之間的效率，進而降低檢測的經濟與時間成本，並加速產品上市時間。
除此之外，由於造成形變的主要原因來自於材料之間的熱膨脹係數不匹配，因此，熱膨脹係數成為評估板彎翹曲至關重要的材料參數；然而欲在實驗中測量得知其參數相對困難且費時，我們介紹了基於物理信息的神經網路(Physics-informed Neural Network, PINN)—藉由監督式學習(Supervised Learning)訓練完成的神經網路，結合已知的材料力學非線性偏微分方程及材料熱應變關係式的約束，將物理信息拓展至網路中。首先，基於前者所敘述之問題，我們利用模擬生成板彎翹曲的數據，給定模型參數，將起始/邊界條件作為輸入及輸出，與傳統的深度學習神經網路相比，研究針對在數據量不足的情況下，對於預測邊界內的物理現象具有更高的準確性，並將預測結果與模擬所獲得的數據集進行比較，說明該方法的可行性。另一方面，將邊界內部的物理信息作為損失函數(Loss function)擴展至神經網路，使模型能夠預測出不易測量的材料參數。

As the electronic devices getting lighter and smaller, a coreless substrate technology, called Embedded Trace Substrate (ETS) is developed to meet the market requirement. However, this design causes severe warpage due to the large difference in CTEs (coefficient of thermal expansion) of build-up material and Cu plate. Recently, finite element analysis (FEA) is a popular and effective method used for substrate warpage prediction and mechanical studies. Manufacturers apply FEA simulation for substrate design improvements, and provide substrate warpage that satisfying the customer’s specification. Nevertheless, the computational resources needed for high-fidelity simulation are extremely expensive and time consuming. Hence the simulation study becomes a long and arduous task if it has to be performed many times, e.g., sensitivity analysis and warpage optimization.
In this paper, three equivalence methods are proposed to reduce the analysis efficiency and difficulty of the finite element analysis (FEA), and three different cases are designed to predict the warpages of substrate through the two software of COMSOL and ANSYS. The results of the method proposed in this paper are consistent and accurate with actual experiments. If this method is applied to the industry in the future, it will be possible to optimize the warpage of the substrate directly by adjusting the parameters in the pretreatment step of the packaging process, which will improve the efficiency between inspection and design, thereby reducing the economy and cost of inspection.
In addition, since the main cause of deformation is the mismatch of thermal expansion coefficients between materials, the thermal expansion coefficient has become a crucial material parameter for evaluating board warpage; Difficult and time-consuming, we introduce the Physics-informed Neural Network (PINN)－a neural network trained by supervised learning (Supervised Learning), combined with the known material mechanics nonlinear partial differential Equations and constraints on material thermal strain relationships extend physical information to the web. First of all, based on the problems described in the former, we use simulation to generate the data of plate bending and warping, given the model parameters, and use the initial/boundary conditions as input and output. Compared with the traditional deep learning neural network, the research is aimed at When the amount of data is insufficient, it has higher accuracy for predicting the physical phenomenon within the boundary, and comparing the prediction results with the data set obtained from the simulation shows the feasibility of the method. On the other hand, extending the physical information inside the boundary as a loss function to the neural network enables the model to predict material parameters that are not easily measurable.

摘要
目錄
第一章 緒論 1
1.1 前言 1
1.1.1 嵌入式基板 3
1.1.2 翹曲與殘留應力 5
1.2 文獻回顧 8
1.3 研究動機與目的 11
1.4 文章架構 12
第二章 研究方法 13
2.1 等效均質理論 15
2.1.1 體積微觀力學方法(volume average micromechanics approach) 16
2.2 材料性質 17
2.2.1 蒲松氏比(Poisson ratio) 18
2.2.2 楊氏係數(Young’s modulus) 18
2.2.3 熱膨脹係數CTE(Coefficient of Thermal Expansion) 20
2.3 統御方程式(Governing Equation) 21
2.4 等效方法(Equivalence method) 25
2.4.1 Layer-Cu%法 26
2.4.2 Zone-Cu%法 26
2.4.3 Trace mapping法 30
2.5 線性與非線性 31
2.5.1 結構非線性 31
2.5.2 幾何非線性 31
2.5.3 材料非線性 32
2.6 Physics-informed Neural Network 33
2.7 回歸模型評估指標 38
第三章 模擬分析與參數估計 40
3.1 模型建立 42
3.1.1 案例一(Layer-Cu%) 46
3.1.2 案例二(Zone-Cu%) 48
3.1.3 案例三(Trace mapping) 50
3.1.4 網格設定 52
3.1.5 邊界條件與初始條件 54
3.2 實驗數據前處理 55
3.2.1 材料參數設定 56
3.2.2 溫度條件 60
3.3 翹曲值預測與參數估計 62
3.3.1 模型建立 62
3.3.2 PINN 66
第四章 結果討論 70
4.1 案例一 72
4.2 案例二 74
4.3 案例三 79
4.4 翹曲值預測 85
4.5 參數估計 90
第五章 結論 91
參考文獻 92



圖目錄
圖一 PCB、IC載板、IC晶片關係圖 1
圖二 嵌入式基板側視圖 3
圖三 UNIT 4
圖四 PANEL、STRIP關係圖 4
圖五 翹曲(Warpage)示意圖，左圖為凸翹曲，右圖為凹翹曲 6
圖六 凸翹曲和凹翹曲的翹曲量計算方式 7
圖七 本研究之嵌入式基板側視圖 13
圖八 FEA模擬系統流程圖 15
圖九 延展性材料應力應變曲線圖 19
圖十 應力應變隨溫度變化圖 20
圖十一 IC載板示意圖 25
圖十二 Zone-Cu%法示意圖 27
圖十三 ODB++設計圖經二質化後轉為高解析度影像 27
圖十四 依照銅線有無區分為1或0 28
圖十五 各層原始線路圖 28
圖十六 10x10 Zone-Cu% 28
圖十七 20x20 Zone-Cu% 29
圖十八 64x64 Zone-Cu% 29
圖十九 Trace mapping示意圖 30
圖二十 彈塑性應力應變曲線 32
圖二十一 左為ReLU函數、右為其一階導數 34
圖二十二 Physics-informed neural network結構示意圖 36
圖二十三 載板幾何及治具的模型三維示意圖 44
圖 二十四 載板幾何與治具俯視圖 44
圖二十五 載板幾何及治具的模型側視圖 45
圖二十六 Layer-Cu%等效示意圖 46
圖二十七 SR Bottom原圖與等效後結果 46
圖二十八 P2原圖與等效後結果 46
圖二十九 FR4原圖與等效後結果 47
圖三十 P1原圖與等效後結果 47
圖三十一 SR Top原圖與等效後結果 47
圖三十二 Zone-Cu%等效示意圖 48
圖三十三 等效細緻化示意圖 49
圖三十四 Trace mapping示意圖 50
圖三十五 SR Top幾何挖空示意圖 51
圖三十六 Trace mapping原理示意圖 51
圖三十七 Trace mapping結果示意圖 52
圖三十八 左為六面體網格、右為四面體網格 52
圖三十九 UNIT網格俯視圖 53
圖四十 UNIT網格側視圖 53
圖四十一 UNIT邊界條件設定位置 54
圖四十二 Solder Mask的楊氏係數與溫度關係圖 55
圖四十三 Solder Mask的CTE與溫度關係圖 55
圖四十四 防焊層楊氏係數與溫度函數(Smoothing) 58
圖四十五 防焊層CTE與溫度函數(Smoothing) 58
圖四十六 材層楊氏係數與溫度函數(Smoothing) 59
圖四十七 材層CTE與溫度函數(Smoothing) 59
圖四十八 製程溫度變化 60
圖四十九 雙層板示意圖 63
圖五十 簡化後的製程溫度條件 64
圖五十一 NN神經網路示意圖 66
圖五十二 輸入層數據示意圖 66
圖五十三 神經網路訓練流程圖 68
圖五十四 UNIT實驗翹曲值圖表 71
圖五十五 各溫度翹曲趨勢 72
圖五十六 Layer-Cu%翹曲值 73
圖五十七 2x2 Zone-Cu%翹曲值 74
圖五十八 4x4 Zone-Cu%翹曲值 74
圖五十九 5x5 Zone-Cu%翹曲值10x10 Zone-Cu%翹曲值 75
圖六十 10x10 Zone-Cu%翹曲值 75
圖六十一 16x16 Zone-Cu%翹曲值 75
圖六十二 20x20 Zone-Cu%翹曲值 76
圖六十三 16x16 Zone-Cu%翹曲趨勢 76
圖六十四 20x20 Zone-Cu%翹曲趨勢 77
圖六十五 案例二所有等效的翹曲值 78
圖六十六 Trace mapping與實驗結果的翹曲值 79
圖六十七 Trace mapping(500um)翹曲趨勢 81
圖六十八 Trace mapping(200um)翹曲趨勢 83
圖六十九 Trace mapping(100um)翹曲趨勢 84
圖七十 上為COMSOL生成的原始數據、下為匯入神經網路數據點 85
圖七十一 不同神經網路的訓練結果 86
圖七十二 沿對角線預測之結果 88



表目錄
表一 UNIT尺寸及材質表 43
表二 治具各方位寬度 43
表三 防焊層材料參數 56
表四 芯材層材料參數 57
表五 溫度條件 61
表六 模型尺寸及材質表 63
表七 模擬中使用的材料性質 63
表八 簡化的溫度條件 65
表九 UNIT實驗翹曲值(單位：μm) 70
表十 兩模型性能表現比較 89
表十一 熱膨脹係數估計 90

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