由於量子電腦擁有比傳統電腦更快速、更有效率的運算方式，所以近年來量子電腦成為現今科技極為重要的發展目標之一。量子位元為量子電腦的基本單位，以其為基礎而衍伸出的結構系統更是五花八門，目前主流的運算系統有量子點、離子井、鑽石空位、超導電路與拓樸量子位元。而此文將利用以約瑟夫森接面為核心的超導電路作為量子晶片的主要架構。

本篇論文利用半導體製程技術將超導電路實現在量子晶片上，其中利用黃光微影與濕式蝕刻製程形成微波共面波導，並利用電子束微影製程與Cross Junction薄膜蒸鍍來製做約瑟夫森接面及量子位元Transmon。

共面波導的設計阻抗為50Ω，製程後的實際阻抗為50.00至50.19Ω。約瑟夫森接面的設計線寬為140nm(設計面積為0.0196平方微米)，製程後的實際線寬為235.5至267.2nm (實際面積為0.0699至0.0746平方微米)，常溫電阻為4.85至5.24kΩ。

Because quantum computers have faster and more efficient computing performance than traditional computers in some situations, quantum computers have become one of the most important development goals of today's technology in recent years. The qubit is the basic unit of a quantum computer, and there are various structural systems derived from it. The current mainstream computing systems include quantum dots, ion wells, diamond vacancies, superconducting circuits, and topological qubits. This article will use the superconducting circuit with the Josephson junction as the key to the quantum chip.

This article uses semiconductor process technology to implement superconducting circuits on chip. Coplanar waveguides are manufactured by photolithography and wet etching processes; the Josephson Junction and Transmon are fabricated by electron beam lithography and Cross Junction thin film evaporation.

The design impedance of the coplanar waveguide is 50Ω, and the actual impedance after processing is 50.00 to 50.19 Ω. The designed line width of the Josephson junction is 140nm , which design area is 0.0196μm^2. The actual line width after the process is 235.5 to 267.2 nm, which actual area is 0.0699 to 0.0746 μm^2, and the normal resistance of Josephson Junction is 4.85 to 5.24 kΩ.

發表聲明書
摘要 i
Abstract ii
誌謝 iii
1 緒論1
1.1 量子位元與量子電腦 1
2 理論背景 3
2.1 約瑟夫森接面 3
2.2 超導量子干涉元件 6
2.3 單一庫柏電子對盒 9
2.4 Transmon 11
2.5 超導量子電路 13
3 製程方法 17
3.1 微波共面波導 18
3.1.1 蒸鍍製程 18
3.1.2 黃光製程 20
3.1.3 蝕刻製程 21
3.2 對準記號 22
3.2.1 黃光製程 22
3.2.2 蒸鍍製程 23
3.2.3 掀離製程 24
3.3 切割破片 25
3.3.1 光阻保護層製程 25
3.3.2 切割破片製程 26
3.4 約瑟夫森接面 28
3.4.1 電子束微影製程 28
3.4.2 蝕刻製程 29
3.4.3 蒸鍍製程 30
3.4.4 掀離製程 34
3.5 量子位元Transmon 36
3.5.1 電子束微影製程 37
3.5.2 蝕刻製程 37
3.5.3 蒸鍍製程 38
3.5.4 掀離製程 38
4 製程及實驗結果 39
4.1 微波共面波導 39
4.1.1 蒸鍍及黃光製程結果 39
4.1.2 蝕刻製程結果 39
4.2 對準記號 40
4.2.1 黃光製程結果 40
4.2.2 蒸鍍及掀離製程結果 42
4.3 約瑟夫森接面 43
4.3.1 電子束微影製程結果 43
4.3.2 蒸鍍及掀離製程結果 44
4.3.3 室溫電阻量測結果 47
4.3.4 電子顯微鏡SEM 量測結果 51
4.4 量子位元 Transmon
4.4.1 電子束微影製程結果 56
4.4.2 蒸鍍及掀離製程結果 56
4.4.3 室溫電阻量測結果 56
4.4.4 電子顯微鏡SEM 量測結果 57
5 結論 61
6 附錄 63
6.1 Plassys MEB550S 蒸鍍機使用手冊 63
6.2 EVG-620 曝光機使用手冊 65
6.2.1 特殊情況(一) 68
6.2.2 特殊情況(二) 69
6.2.3 特殊情況(三) 70
6.3 Elionix ELS-7800 電子束微影機台代工手冊 70
6.4 SAMCO PC-300 電漿清洗機使用手冊 72
6.4.1 特殊情況(一) 74
6.5 JSM-7000F 電子顯微鏡使用手冊 74
6.6 實驗用品耗材 77
References 81

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