隨著科技日新月異，雲端網絡、大數據以及物聯網發展日趨成熟，改變了全球產業和社會。近年來半導體產業快速崛起，然而隨著摩爾定律的微縮，傳統的 FinFET 製程技術將受到限制，也面臨了許多物理極限的挑戰與製程技術的困難，因此如何克服這些問題成為了目前至關重要的議題。為了延續摩爾定律，許多研究學者提出未來可以選用高遷移率的半導體材料(如：鍺、三五族化合物)取代傳統的矽作為通道材料，或是將二維結構的電晶體以三維結構呈現，甚至近一步發展成堆疊結構，期望提高元件性能。
本論文利用自我對準(Self-aligned)製程技術製作P型鍺奈米線通道結構垂直堆疊在N型矽鰭式通道結構上之互補式場效電晶體(Complementary Field-Effect Transistor, CFET)，元件尺寸可微縮百分之五十。此外也利用單一雙層 60 nm TaN（下層）/30 nm TiN（上層）作為N型Si-FinFET以及P型Ge-GAAFET之閘極金屬，並以低溫微波退火及自我分離汲極/源極摻雜活化技術，達到異質通道材料整合。在金屬功函數調變上採用兩種方式，分別為不同閘極氧化層堆疊與不同閘極金屬。我們發現利用不同閘極金屬可使金屬功函數有顯著的變化，因此在Si nFinFET與Ge pFinFET上，均使用不同的閘極金屬TaN和TiN來調變臨界電壓(VTH)。Si nFinFET的VTH變化量為0.65(V), 而Ge pFinFET的VTH變化量為0.15(V)。
最後我們將TiN/TaN/Al2O3閘極氧化層結構應用於CFET結構之N型Si-FinFET以及P型Ge-GAAFET。N型 Si-FinFET與P型Ge-GAAFET在|VD| = |VG-VTH| = 0.5V時，分別獲得ION=70𝜇A/𝜇m與194𝜇A/𝜇m，而在|VD| = 0.05V時，則獲得SSMIN = 91mV/dec與74mV/dec。並根據CFET 模擬，當金屬功函數為4.38(eV) 時，N型Si-FinFET以及P型Ge-GAAFET具有對稱的VTH及ION。因此可以大幅提升元件性能，並延續摩爾定律。

With the advancement of science and technology, the evolution of cloud networks, big data, and the Internet of Things (IoT) change the global industry and society. The semiconductor industry has rapidly developed in recent years. However, as Moore's Law continues scaling, the conventional FinFET technology will hit limitations. It comes from the challenges of many devices’ physical limits and the difficulties of process technology. Therefore, how to overcome these problems is a crucial issue. To extend Moore’s Law scaling, high mobility semiconductor materials (such as germanium, and III-V compounds) can be proposed to replace silicon as channel materials. Meanwhile, replacing the horizontally two-dimensional MOSFET transistor with a vertically three-dimensional stacked transistor structure presents a promising alternative for extending CMOS application.
In this thesis, we use self-aligned technology to fabricate the complementary field-effect transistor (CFET) with the Ge NW p-channel GAAFET vertically stacked on the Si n-channel FinFET. The inverter cell area can be reduced by 50 %, comparing to standard CMOS. In addition, the single bilayer 60 nm-thick TaN (bottom) / 30 nm-thick TiN (top) metal gate is used as the N-type Si-FinFET and P-type Ge-GAAFET. Adapting low-temperature microwave annealing (MWA) and self-separated drain/source(S/D) doping activation achieve heterogeneous channel materials in CFET integration. In addition, two methods to modulate the metal work function(Φm), different gate oxide stacks and different gate metals were studied. We found that using different gate metals can significantly modulate Φm, therefore different gate metals TaN and TiN were both used in Si nFinFET and Ge pFinFET to modulate the threshold voltage (VTH). Si nFinFET presents |ΔVTH|=0.65(V), and Ge pFinFET shows |ΔVTH|= 0.15(V).
Finally, we fabricate Ge pGAAFET and Si nFinFET of the CFET structure with a common TiN/TaN/Al2O3 gate oxide stack structure. Si nFinFET presents ION=70𝜇A/𝜇m at |VD|=|VG-VTH|=0.5V and shows SSMIN=91mV/dec at |VD|=0.05V. Ge pGAAFET presents ION=194𝜇A/𝜇m at |VD|=|VG-VTH|=0.5V and shows SSMIN=74mV/dec at |VD|=0.05V. According to the CFET 3D TCAD simulation, when the Φm is 4.38 (eV), Si nFinFET and Ge pGAAFET show symmetrical VTH and ION. As a result, this studied CFET can be greatly improved and promises flexibility for extending Moore’s Law scaling.

中文摘要---------i
Abstract---------iii
誌謝---------v
目錄---------vi
表目錄---------viii
圖表目錄---------ix
第一章---------1
簡介---------1
1-1 摩爾定律 (Moore's law)---------1
1-2 高載子遷移率之通道材料---------4
1-3 氧化層厚度的微縮---------5
1-4 3D垂直堆疊互補式場效電晶體結構---------8
1-5 低溫微波退火---------11
1-6 霍爾量測---------13
1-7 研究動機---------14
1-8 論文組織---------19
第二章---------21
MOSFET與CMOS操作機制與重要參數---------21
2-1 MOSFET與CMOS反相器操作機制---------21
2-2 MOSFET重要參數---------25
第三章---------28
MIS電容結構之製作與特性分析---------28
3-1 矽與鍺異質通道材料整合---------28
3-2 金屬閘極之功函數調變---------36
第四章---------50
自我對準垂直堆疊互補式電晶體---------50
4-1 不同金屬閘極之鰭式場效電晶體電性比較---------50
4-2 互補式場效電晶體之特性---------56
4-3 單一金屬/high-k閘極堆疊互補式電晶體之模擬---------67
第五章---------70
結論---------70
參考文獻---------72

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