本論文旨在設計並量測一類比數位轉換器，架構為連續漸進式，規格為十二有效位元、每秒一千萬次採樣。連續漸進式架構多以電容組成內部數位類比轉換器，帶來的詬病便是過大的面積及功耗。為減輕此種問題，本論文採用單調向下的切換機制以減少電容的面積及其功耗，並以自我比較器修正來減輕其電壓準位在位元轉換過程中不斷下降所帶來的偏移問題。

晶片使用TSMC 0.18 μm 1P6M CMOS製程實現，總面積為0.8 mm2，不含PAD之核心晶片面積為0.28 mm2，供應電壓為1.8 V、採樣頻率為每秒一千萬次、輸入差動弦波頻率在接近5 MHz、1.8 V振幅下之佈局前模擬結果，其有效位元數達到11.66，平均功耗為0.524 mW，INL與DNL之靜態模擬結果分別為( 1.49 / -1.88 LSB) 與 ( 2.14 / -1.00 LSB)，量測可得最高有效位元數為7.78，於輸入訊號頻率700 Hz、採樣頻率900 kHz測得。

This paper presents an analog-to-digital converter(ADC), which is based on successive approximationn register structure(SAR). The specifications of the ADC is 12-bit ENOB and 10MS/s.

Most of the SAR ADC use capacitance to build the DAC inside, which leads to larger area and power comsumption. To reduce its effect, the designed ADC uses monotonic switch mechanism and self-calibration of comparators to reduce the changing offset issue induced by voltage level going down during bits conversion phase.

The chip is implemented under the TSMC 0.18 μm 1P6M CMOS process. The total chip area, including IO pads, is 0.8mm2 and the core circuit occupies 0.28 mm2. The supply voltage is 1.8 V, sampling frequency is 10 MHz. The pre-layout-simulation for input signal of almost 5 MHz, 1.8 Vpp shows 11.66 ENOB, 0.524 mW power consumption, the static simulation shows INL and DNL of (1.49/-1.88 LSB) and (2.14/-1.00 LSB). The highest ENOB measured is 7.78, which is measured with input frequency of 700 Hz, sampling frequency of 900 kHz.

摘要 I
致謝 III
目錄 V
圖目錄 VII
表目錄 IX
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文章節架構 4
第二章 研究介紹與架構說明 5
2.1 類比數位轉換器參數介紹 5
2.2 類比數位轉換器架構說明 7
2.2.1 連續漸進式類比數位轉換器 7
2.2.2 傳統切換機制 10
2.2.3 單調向下切換機制 14
第三章 電路架構設計與探討 17
3.1 數位類比轉換器 17
3.2 採樣保持電路 19
3.3 動態比較器電路 23
3.4 非同步控制邏輯 27
3.5 邏輯切換電路 29
3.6 偏差消除電路 31
3.7 類比數位轉換器 35
第四章 模擬與佈局 38
4.1 佈局前模擬 38
4.1.1 採樣保持電路 38
4.1.2 動態比較器電路 40
4.1.3 偏移消除電路 44
4.1.4 總系統模擬 46
4.2 佈局後模擬 48
4.2.1 採樣保持電路 48
4.2.2 動態比較器電路 49
4.2.3 總系統模擬 51
4.3 晶片佈局 60
4.4 預計規格與模擬結果比較 61
4.5 文獻比較 62
第五章 量測與討論 63
5.1 印刷電路板設計與量測環境 63
5.2 量測結果與討論 65
第六章 總結與研究建議 73
6.1 總結 73
6.2 研究建議 74
6.2.1 模擬與佈局部分 74
6.2.2 量測部分 74
參考文獻 75

[1] Walt Kester, “Which ADC Architecture Is Right for Your Application? ”
Analog Dialogue 39 - 06, June 2005

[2] Jacob Baker, "CMOS Circuit Design, Layout, and simulation ", 2010

[3] F. Kuttner, "A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-m CMOS," in IEEE ISSCC Dig. Tech. Papers, pp. 176-177, 2002.

[4] Chun-Cheng Liu, Soon-Jyh Chang, Member , Guan-Ying Huang, Ying-Zu Lin,
“A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching,”
IEEE Journal of Solid-State Circuits, vol. 45, no. 4 , April 2010, pp. 731 - 740.

[5] B. Razavi, Design of Analog CMOS Integrated Circuit. 2001

[6] A. M. Abo, P. R. Gray, "A 1.5-V 10-bit 14.3-MS/s CMOS pipeline analog-to-digital converter", IEEE Journal of Solid-State Circuits, vol. 34, no. 5, May 1999, pp. 599-606.

[7] B. Razavi, Principles of Data Conversion System Design. 1995

[8] A. Khorami and M. Sharifkhani, "A low-power high-speed comparator for precise applications", IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 26, no. 10, Oct. 2018, pp. 2038-2049.
[9] A. Khorami, M. B. Dastjerdi and A. F. Ahmadi, "A low-power highspeed comparator for analog to digital converters", 2016 IEEE International Symposium on Circuits and Systems (ISCAS), May 2016, pp. 2010-2013.

[10] A. Nikoozadeh and B. Murmann, "An analysis of latch comparator offset due to load capacitor mismatch", IEEE Trans. Circuits Syst. II Express Briefs, vol. 53, no. 12, pp. 1398-1402, Dec. 2006.

[11] 吳俊曄, 徐永珍, “一個具有1.3 mW平均功耗、10 MHz取樣速率、12-ENOB的雜訊重塑連續漸進式類比數位轉換器”國立清華大學, 電子工程研究所, 碩士論文, 中華民國一百零九年十月

[12] 陳冠彣, 徐永珍, “標準0.18 mmCMOS製程中整合二階式單斜率類比數位 轉換器之影像感測電設計”國立清華大學, 電子工程研究所, 碩士論文, 中華民國一百零五年十二月

[13] Masaya Miyahara, Yusuke Asada, Daehwa Paik, Akira Matsuzawa, “A low-noise self-calibrating dynamic comparator for high-speed ADCs,”
IEEE Asian Solid-State Circuits Conference, pp. 269-272, 2008.

[14] A. Graupner, "A Methodology for Offset Simulation of Comparators", The Designer Guide Community, Oct. 2006.




[15] N. Verma and A. P. Chandrakasan, “An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes,” IEEE Journal of Solid-State Circuits, vol. 42, no. 6, June 2007, pp. 1196 - 1205.

[16] Min-Kyu Kim, Seong-Kwan Hong, Oh-Kyong Kwon ," An Area-Efficient and Low-Power 12-b SAR/Single-Slope ADC Without Calibration Method for CMOS Image Sensors" IEEE Transactions on Electron Devices, vol. 63, no. 9, September 2016, pp. 3599 - 3604.

[17] F. Tang, D. G. Chen, B. Wang, and A. Bermak, "Low-Power CMOS Image Sensor Based on Column-Parallel Single-Slope/SAR Quantization Scheme "
IEEE Transactions on Electron Devices, vol. 60, no. 8, August 2013, pp. 2561–2566.

[18] D. G. Chen, F. Tang, M.-K. Law, and A. Bermak, "A 12 pJ/pixel Analog-to-Information Converter Based 816 × 640 Pixel CMOS Image Sensor " IEEE Journal of Solid-State Circuits, vol. 49, no. 5, May 2014, pp. 1210–1222.

[19] Yue Wu, Xu Cheng, Xiaoyang Zeng, “A split-capacitor VCM-based capacitor-switching scheme for low-power SAR ADCs”, 2013 IEEE International Symposium on Circuits and Systems (ISCAS)

[20] Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, S.-P. U. R. P. Martins, F. Maloberti, "A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS",
IEEE Journal of Solid-State Circuits, vol. 45, no. 6, Jun. 2010, pp. 1111-1121.