本論文利用在多個影像感測電路上設計不同感測架構，比較並探討不同感光元件與電路區塊對於感測動態範圍之影響。測試電路中的設計差異包含：感光元件使用光伏模式(Photovoltaic Mode)之光二極體或橫向光電晶體、像素讀取電路使用n-MOSFET或p-MOSFET、於像素陣列後是否加入讀取行放大器(Column Amplifier)。在本論文中會提出標準CMOS製程中影像感測電路的特殊後模擬方式，建立光伏模式影像感測器的雜訊量測技術，並根據不同量測環境下的雜訊量值分析各子電路的輸出雜訊貢獻。
目前市面上的影像感測器多以操作在逆偏壓之光二極體作為感光元件，在此操作模式下為了解析弱光像素的訊號會延長曝光時間，因此容易在強光像素發生二極體位能井的電荷飽和而產生過曝的現象。為解決上述效應，影像感測裝置通常會進行多次取樣(Multiple Sampling)並根據多張不同曝光時間下的影像進行後期處理，以得到高動態範圍的影像，但如此影像感測技術會消耗更多時間完成單張影像的拍攝。本研究將光感測元件操作在開路的光伏模式，由於該模式讀取之感測元件電壓(光電壓)為光電流與順向電流達到穩態後的電壓，故此操作模式下較不易發生位能井飽和的狀況，能有效提升電路之飽和光強度。
從量測上可以觀察到光伏模式之對數響應所帶來的飽和光強度提升，故本研究將以雜訊等效光強度(Noise Equivalent Intensity, NEI)作為感測動態範圍的主要改善指標。根據量測結果能觀察到：相較於使用光二極體與P-MOSFET讀取像素之感測電路，若額外加入讀取行放大器可減少約10%的雜訊等效光強度；若將光感測元件替換為橫向光電晶體則可再減少50%的雜訊等效光強度。未來若針對光電晶體之輸出電壓進行感測電路的進一步優化，可期待得到更低的雜訊等效光強度與更多的動態範圍提升。

This thesis studies the effect of different photodetectors and readout circuit combinations on CMOS image sensor dynamic range by testing circuits with various building blocks. The proposed selection of building blocks contains: utilizing photodiodes (PD) or lateral phototransistors (LPT) as photodetectors, n-MOSFETs or p-MOSFETs as transistors in pixel level readout circuits, and whether applying column-level gain with column amplifiers. During the research progress, CMOS image sensor post-simulation method, photovoltaic mode image sensor noise measuring techniques, and analyzing procedure of image sensor sub-circuits noise contribution will be proposed.
Most commercial CMOS image sensors utilize reverse-biased photodiodes as photodetectors; nevertheless, if one extends exposure time to analyze signal in low light pixels under such operation mode, photo-charges may fill potential wells of photodetectors in strong light pixels, thus leads to overexposure of those pixels. In order to resolve the issue, most image sensor designers utilize multiple sampling technique, which means acquiring high dynamic range images by performing post-processing with multiple raw images using different exposure time; however, the total exposure time may be extended due to the requirement of multiple raw images. This work focuses on photodetectors in photovoltaic mode, owing to the physics that under photovoltaic operation mode, photovoltage output is referred to the balance of photocurrent and forward-biased photodetector current but not related to full-well capacity, the saturation illuminance of photovoltaic mode photodetectors can be considerably enhanced.
Because the saturation illuminance of photodetectors in photovoltaic mode is too large to be observed in the measurement, this work takes noise-equivalent intensity (NEI) as parameter to represent the enhancement of dynamic range. Compared with test circuits utilizing only PD as photosensors and p-MOSFET pixel readout circuits before column sampling circuits, placing an additional column amplifier after pixel readout circuit can bring to 10% of NEI reduction, further replaces PD with LPT can lead to another 50% of NEI reduction. If all sensing circuits can be optimized with LPT light response, more NEI reduction and dynamic range enhancement can be expected. 

目錄
摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vii
表目錄 xii
第一章 前言 1
1.1 近代影像感測器產業的發展 2
1.2 研究動機 6
第二章 CMOS影像感測器簡介 8
2.1 CMOS影像感測器的基本架構 8
2.2 常用的光感測元件 9
2.3 光感測元件的操作模式 11
2.4 光訊號之讀取電路 13
2.5 評比影像感測器表現之重要參數 16
第三章 高動態範圍影像感測器的發展 17
3.1 減少輸出雜訊以擴展動態範圍的方式 17
3.1.1 埋入通道源極隨耦器 18
3.1.2 薄氧化物PMOS源極隨耦器 19
3.1.3 共源極PMOS像素放大器 20
3.1.4 高讀取行增益 21
3.1.5 相關多重取樣 22
3.2 增加飽和準位以擴展動態範圍的方式 23
3.2.1 溢流汲極 24
3.2.2 對數響應電路 25
3.2.3 光伏模式感測 26
3.2.4 頻率脈衝調變 27
3.2.5 飽和計數 28
3.2.6 多次取樣 29
第四章 測試晶片架構與使用電路 30
4.1 測試晶片使用之電路架構 30
4.1.1 類比電路 30
4.1.2 數位電路 32
4.2 提高動態範圍的元件與電路設計 36
4.3 晶片上各測試組之差異 40
第五章 測試晶片之設計、模擬與佈局 42
5.1 測試電路之設計與佈局 44
5.2 測試電路之前模擬結果 57
5.3 含自訂光偵測元件之電路的後模擬 62
第六章 量測架構與量測結果 65
6.1 測試晶片使用之印刷電路板設計 65
6.2 影像感測電路之量測架構 66
6.3 測試電路之量測結果分析與討論 69
6.3.1 光二極體與PMOS讀取像素之量測結果 70
6.3.2 橫向光電晶體PMOS讀取像素之量測結果 74
6.3.3 讀取行放大器的量測結果 81
6.3.4 光二極體與PMOS讀取像素之感測電路量測結果 82
6.3.5 具讀取行放大的光二極體與PMOS讀取像素之感測電路量測結果 83
6.3.6 具讀取行放大的光電晶體PMOS讀取像素之感測電路量測結果 86
6.3.7 使用NMOS讀取像素之感測電路量測結果 87
6.3.8 光二極體與PMOS讀取像素之影像感測電路定格雜訊觀察 88
6.3.9 各項感測電路的雜訊量測 89
6.3.10 本研究中使用之感測電路效能比較 90
第七章 結論與後續研究建議 94
7.1 結論 94
7.2 後續研究建議 96
第八章 參考資料 98

[1] Yole Development. (2018). Status of the CMOS Image Sensor Industry 2018 report sample [Online]. Available: https://www.bath.ac.uk/publications/library-guides-to-citing-referencing/attachments/ieee-style-guide.pdf
[2] D. Litwiller, “CCD vs. CMOS: Facts and fictions,” Photonics Spectra, 2001
[3] 雷良煥, 黃吉成, 徐永珍, “後來居上的CMOS 影像感測器,” 物理雙月刊32卷1期, 2010
[4] S. Guissi. (2017). CMOS Image Sensors (CIS): Past, Present & Future [Online]. Available: https://www.coventor.com/blog/cmos-image-sensors-cis-past-present-future/
[5] Canon News. (2019). Future Canon sensor technology - an overview [Online]. Available: https://www.canonnews.com/future-canon-sensor-technology-an-overview
[6] iSUPPLi; IDC; strategies unlimited; JPMorgan; Micron Marking, 2005
[7] C. Rose, R. Butler, R. Sanyal. (2017). Nikon D850 Review [Online]. Available: https://www.dpreview.com/reviews/nikon-d850
[8] S. J. Capistrano. (2013, Apr. 4). IQinVision Announces Full Array Of Wide Dynamic Range Cameras [Online]. Available:
https://www.varinsights.com/doc/iqinvision-announces-full-array-of-wide-dynamic-range-cameras-0001
[9] M. Sasaki, M. Mase, S. Kawahito, and Y. Tadokoro, “A wide dynamic range CMOS image sensor with multiple short-time exposures,” in Proceedings of IEEE Sensors, Oct. 2004, pp. 967-972
[10] H. Tian, “Noise Analysis in CMOS Image Sensors,” Ph.D. dissertation, Dept. Applied Phys., Stanford University, 2000
[11] PVEducation. Absorption Coefficient. [Online]. Available: https://www.pveducation.org/pvcdrom/pn-junctions/absorption-coefficient
[12] J. Ohta, Smart CMOS Image Sensors and Applications, CRC Press, 2007
[13] I. Brouk, A. Nemirovsky, Y. Nemirovsky, "Analysis of noise in CMOS image sensor," in IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems, 2008, pp.I-8
[14] Y. Chen, Y. Xu, Y. Chae, A. Mierop, X. Wang, and A. Theuwissen, “A 0.7e-rms-temporal-readout-noise CMOS image sensor for low-light-level imaging,” in IEEE International Solid-State Circuits Conference, Feb. 2012, pp. 384-386
[15] Y. Chen, J. Tan, X. Wang, A. J. Mierop, and A. J. P. Theuwissen, “In-pixel buried-channel source follower in CMOS image sensors exposed to X-ray radiation,” in Proceedings of IEEE Sensors, Nov. 1-4 2010, pp. 1649-1652
[16] A. Boukhayma, A. Peizerat, and C. Enz, “Temporal Readout Noise Analysis and Reduction Techniques for Low-Light CMOS Image Sensors,” IEEE Transactions on Electron Devices, vol. 63, no. 1, pp. 72-78, Jan. 2016.
[17] C. Lotto, P. Seitz, and T. Baechler, “A sub-electron readout noise CMOS image sensor with pixel-level open-loop voltage amplification,” in 2011 IEEE International Solid-State Circuits Conference, Feb. 2011, pp. 402-404
[18] N. Kawai and S. Kawahito, “Noise analysis of high-gain, low-noise column readout circuits for CMOS image sensors,” IEEE Transactions on Electron Devices, vol. 51, no. 2, pp. 185-194, Feb. 2004
[19] Y. Chen, Y. Xu, Y. Chae, A. Mierop, X. Wang, and A. Theuwissen, “A 0.7e−rms-temporal-readout-noise CMOS image sensor for low-light-level imaging,” in IEEE International Solid-State Circuits Conference, Feb. 2012, pp. 384-386
[20] M.-W. Seo, T. Sawamoto, T. Akahori, T. Iida, T. Takasawa, K. Yasutomi, and S. Kawahito, “A low noise wide dynamic range CMOS image sensor with low-noise transistors and 17b column-parallel ADC,” IEEE Sensors Journal, vol. 13, no. 8, pp. 2922-2929, Aug. 2013
[21] N. Ide, N. Akahane, S. Sugawa, “A Linear Response 200-dB Dynamic Range CMOS Image Sensor with Multiple Voltage and Current Readout Operations”, Proceeding of SPIE-IS&T Electronic Imaging, SPIE Vol. 6816, 681605s, Feb. 2008
[22] N. Akahane, S. Sugawa, S. Adachi, K. Mori, T. Ishiuchi, and K. Mizobuchi, “A sensitivity and linearity improvement of a 100-db dynamic range cmos image sensor using a lateral overflow integration capacitor,” IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 851-858, Apr. 2006
[23] S. Kavadias, B. Dierickx, D. Scheffer, A. Alaerts, D.Uwaerts, and J. Bogaerts, “A logarithmic response CMOS image sensor with on-chip calibration, ” IEEE Journal of Solid-State Circuits, vol. 35, no.8, pp. 1146-1152,Aug. 2000
[24] Y. Ni, Y. Zhu, and B. Arion, “A 768×576 logarithmic image sensor with photodiode in solar cell mode,” in Proceeding of International Image Sensor Workshop, 2011, pp. 1-4
[25] W. Yang, “A wide-dynamic-range low-power photosensor array,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, 1994, pp. 230-231
[26] T. Lulé, B. Schneider, and M. Böhm, “Design and fabrication of a high dynamic range image sensor in TFA technology,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 704-711, May 1999
[27] M. Sasaki, M. Mase, S. Kawahito, and Y. Tadokoro, “A wide dynamic range CMOS image sensor with multiple short-time exposures,” in Proceeding of IEEE Sensors, Oct. 2004, pp. 967-972
[28] 蔡昀廷,“標準 CMOS 製程中橫向 NPN 電晶體於高動態範圍影像偵測器之應用", 國立清華大學, 電子工程研究所, 碩士論文, 中華民國一百一○年一月
[29] 林祐玄, “標準製程下實現高響應度橫向光感測電晶體之研究", 國立清華大學, 電子工程研究所, 碩士論文, 中華民國一百零六年十月
[30] X. Ge, “A CMOS Image Sensor with Nearly Unity-Gain Source Follower and Optimized Column Amplifier”, IEEE Sensors, 2016
[31] Christian Enz et al.,“A Sub-0.5 Electron Read Noise VGA Image Sensor in a Standard CMOS Process”, IEEE Journal of Solid-State Circuits, July 2016
[32] 李律,“0.18μm 標準 SiGe BiCMOS 製程之高動態範圍影像感測電路設計", 國立清華大學, 電子工程研究所, 碩士論文, 中華民國一百零八年一月
[33] S. Suh, S. Itoh, S. Aoyama, and S. Kawahito, “Column-parallel correlated multiple sampling circuits for CMOS image sensors and their noise reduction effects,” Sensors, vol. 10, no. 10, pp. 9139-9154, 2010
[34] C. Saint, J. Saint, “IC Mask Design: Essential Layout Techniques,” 2002
[35] Silvaco. A 3D Diode Simulation with Small Signal Optical AC Analysis. [Online]. Available: https://Silvaco.com/examples/tcad/section26/example13/index.html
[36] Silvaco. ATLAS User Manual. [Online]. Available: https://www.eng.buffalo.edu/~wie/Silvaco/atlas_user_manual.pdf
[37] A. Novikov, “Experimental measurement of work function in doped silicon surfaces,” Solid-State Electronic Journal, vol. 54, pp. 8–13, Jan. 2010
[38] R. T. Tung, “The physics and chemistry of the Schottky barrier height,” Applied Physics Review, vol. 1, no. 1, pp. 011304, 2014
[39] G. Çankaya, N. Ucar, “Schottky Barrier Height Dependence on the Metal Work Function for p-type Si Schottky Diodes,” Zeitschrift fur Naturforschung, Nov. 2004
[40] C. T. Tai, M. D. Ker, “Optimization of Guard Ring Structures to Improve Latchup Immunity in an 18 V DDDMOS Process,” IEEE Transactions on Electron Devices, vol. 63, no. 6, pp. 1-6, June. 2016.