對於一個主要任務為監控與紀錄環境及生理資料的穿戴式醫療裝置而言，在要求多個感測器
以高採樣率收集資料的情況下，會對處理器使用率造成極大的負擔，可能會導致可排程性的
喪失。對於像資料蒐集這樣的規律性作業，本論文提出一種可以大幅減少處理器使用率的排
程設計，運用新型微控制器上所搭載的鏈結式直接記憶體存取(Linked DMA, LDMA)，將原
本由處理器所執行的一系列指令，儘可能交由LDMA去自動化完成，以實現一個低處理器使
用率的硬實時系統(hard real-time system)。在這樣的系統中，我們同時考慮LDMA 通道的使
用率，並嘗試了兩種設計: 處理器使用率最佳化設計及負載平衡設計。在處理器使用率最佳
化設計中，本論文將實例系統的六個任務中的四個任務轉換為可以完全交由LDMA控制器來
執行，而不需要處理器介入的形式，將原本處理器使用率為63.1%的系統降至了19.1%，並且
佔用了所有的LDMA通道。考量到LDMA通道也是一種有限資源，本論文提出了LDMA任務
排程器進行LDMA通道的資源分配，實現LDMA通道的重用性，並應用在負載平衡設計中，
大幅減少LDMA通道使用率。

This thesis presents a scheduling scheme that maximizes offloading of hard real-time tasks onto linked
direct memory access (LDMA) hardware on modern microcontroller units (MCU). These tasks are
characterized by data collection of vital signs that must be sampled at relative high rates but otherwise
have relatively low computation load to perform. Conventional processors are poorly matched
with such loads, because they must service parallel data-collection tasks by context switching among
them as triggered by either a timer or a data-ready interrupt, all without using the computing capability
of the processor. This thesis describes a case study of a wearable medical device that takes
full advantage of LDMA to achieve the most efficient implementation on the MCU. This thesis proposes
two designs: the processor-LDMA co-optimization design and the load-balancing design. The
processor-LDMA co-optimization design reduce the processor utilization from 63.1% to 19.1% with
LDMA channels fully occupied. This thesis also proposes the load-balancing design using our proposed
LDMA task scheduler to significantly reduce the LDMA channel utilization while maintaining
low processor utilization (19.2%).

Contents i
Acknowledgments vi
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Background and Related Work 4
2.1 Input/Output (I/O) Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.1 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.2 Interrupt I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.3 Direct Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Enhanced DMA Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 Designs Using Advanced DMA . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.2 Processor-DMA Co-Scheduling . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Common Bus Protocols for Embedded Systems . . . . . . . . . . . . . . . . . . . . 7
2.3.1 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.2 Inter-Integrated Circuit (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Real-Time Operating Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4.1 Types of Real-Time Systems . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4.2 Rate Monotonic Scheduling (RMS) . . . . . . . . . . . . . . . . . . . . . . 10
2.4.3 Earliest Deadline First (EDF) . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.5 Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Motivating Example: BlueBox 13
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Sampling-Rate and Bit-Resolution Requirements . . . . . . . . . . . . . . . . . . . 16
4 Linked Direct Memory Access (LDMA) 17
4.1 Channel Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.1 Types of Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.2 Descriptor Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.3 Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.4 Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 LDMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2.1 Trigger Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.2 Looping Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.3 Channel Mechanism Overview . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 LDMA Task Scheduler 22
5.1 LDMA Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 Multiplexing LDMA Channels Among LDMA Tasks . . . . . . . . . . . . . . . . . 23
5.3 The LDMA Task Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.1 Channel Allocation Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.2 Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3.3 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3.4 Task Enter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3.5 Task Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.6 Task End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.7 Context Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.8 Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.9 Channel Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.10 Channel Schedulability Analysis . . . . . . . . . . . . . . . . . . . . . . . . 30
6 Evaluation 31
6.1 RTOS Applications of BlueBox . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1.1 Task Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1.2 Schedulability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.1.3 Task Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2 Converting RTOS tasks into LDMA tasks . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.1 Loop Type and Non-loop Type . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2.2 ADS1298R-Sampling Task . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2.3 LED Signal Control Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2.4 Data-Gathering Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2.5 Flash-Writing Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3 Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3.1 Processor-LDMA Co-Optimization Design . . . . . . . . . . . . . . . . . . 45
6.3.2 Load-Balancing Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7 Conclusions and Future Work 47
7.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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