在傳統的製程當中，電路被設計成單一列高且標準電路元件也與列同高，隨著標準電路元件的複雜化，與列同高的元件已無法滿足。為了滿足時序限制，關鍵時序之元件會使用列高較高之標準元件庫，因為列高較高之元件有較強的驅動能力，然而，其面積較大且功率耗損也較多，況且並非所有元件皆為關鍵時序之元件。所以若是所有元件皆使用列高較高之標準元件會導致晶片擺放的整體面積增加和功率耗損增加。為了達到面積以及效能之間的平衡，我們使用混和列高度元件的設計，且每個標準元件有不同高度、寬度的版本選擇，依據標準元件的效能需求而選擇。

在本論文中，我們試著對混合列高之元件進行細部擺置，以求減少繞線線長和溢流。在減少繞線線長方面，受到optimal region (最佳區塊)的啟發，我們試著把標準元件移到最佳區塊，並在最佳區塊不夠標準元件擺放時進行區塊壓縮或標準元件的版本變換。在減少溢流方面則提出擴大分散溢流範圍的演算法來分散標準元件，在減少溢流和繞線線長增長之下達平衡。實驗結果顯示：在合理的時間範圍內我們可以縮短混合列高之設計的繞線線長，且在不增加太多繞線線長的情況下減少設計的溢流。

In a traditional cell-based design, the circuit is divided into uniform-height rows and comprises standard cells which have the same height as the row. However, uniform-row-height cells can no longer satisfy complex design requirements. In order to meet timing constraints, the timing-critical cells will use a standard cell library with a taller cell height, because the cells of taller height have stronger driving capabilities. However, they have a larger area and more power consumption. Moreover, not all the cells are timing-critical. Therefore, if all cells are of taller heights, the overall area and power consumption will increase. In order to achieve a balance between area, performance, and power, mixed-row-height designs have been recently proposed. The placement region for each of such designs is divided into rows of two different heights, and short rows and tall rows are arranged in an interleaving manner. Each cell in the design has one of three possible heights.

In this thesis, we present a detailed placement methodology to reduce wirelength and overflow bins for mixed-row-height designs. To reduce wirelength, inspired by the concept of optimal region, we try to move cells to optimal regions and perform region compression or cell version change when each white space of an optimal region is not large enough for a cell to move in.
To reduce bin overflow, a method to expand the region of overflow bins is proposed to spread cells and achieves a balance under the reduction of overflow bins and wirelength growth. The experimental results show that we can not only shorten the wirelength of a mixed-row-height design with a reasonable runtime but also reduce the number of overflow bins.

1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.2 Previous Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.3 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2 Problem Formulation 5
2.1 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.1.1 HPWL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.1.2 Bin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.1.3 Optimal Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2 Problem Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3 Methodology 10
3.1 Overall Working Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.2 HPWL­-Optimized Method . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2.1 Get the Revised Optimal Region . . . . . . . . . . . . . . . . . . . . .13
3.2.2 Shift Optimal Region’s Cells . . . . . . . . . . . . . . . . . . . .15
3.2.3 Cell Version Change . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.3 Density­-Optimized Method . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.3.1 Find Congested Bin and Expand the Range . . . . . . . . . . . . . . . .23
3.3.2 Calculate Approximately Average Gap Width for the Primary Cells . .24
3.3.3 Move the Primary Cells and Other Cells . . . . . . . . . . . . . . . . .27
4 Experimental Results 28
4.1 Experiment Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.2.1 Analysis of the Experiment of the HPWL-­optimized Method . . . . . . .33
4.2.2 Analysis of the Experiment of the Density­-optimized Method . . . . . .40
5 Conclusion 45
References 46

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