隨著科技的進步，電子產品的設計變得越來越複雜。為了提升電子產品的效能，電子產品必須提高運作時脈以增加計算速度。當運作時脈變得越高來越高時，訊號的傳遞時間顯得至關重要。若每條訊號線的傳遞時間不同，會導致元件接收到錯誤的訊號，因此我們必須調整訊號線到相同長度，以控制不同訊號的傳遞時間差在可接受的範圍之內。以主機板為例，連接中央處理器與記憶體間的關鍵訊號線動輒上百條，且訊號線之間必須滿足複雜的長度匹配規則以維持訊號的正確性。目前主機板上的訊號線主要仰賴人工完成繞線，雖然人工繞線可以達到百分之百的完成率，可是需要花費大量時間微調訊號線的長度，且有可能在調整長度時違反其他設計規則。為了縮短人工微調線長所耗費的時間，本論文提出了一個用於印刷電路板的長度匹配調整演算法。本演算法以人工繞線結果為基礎，先計算每條訊號線需要調整的長度，再實際調整訊號線以解決長度匹配問題。為了精準控制訊號線與障礙物的距離，我們改用幾何計算的方式直接計算距離，以消除將訊號線與障礙物放上網格所造成的誤差。實驗結果表明，我們的方法可以在數秒內計算每條訊號線需要調整的長度並完成訊號線的調整，調整成功率可達百分之七十五且不會違反設計規則。

With the progress of technology, the design of electronic products has become more and more complex. To improve the performance of electronic products, the electronic products must increase the clock rate to speed up the calculation. As the clock rate becomes higher and higher, the timing of the signal transmission becomes more critical. Different transmission time for each net can cause the integrated circuits to receive the wrong signal, so we must adjust the net to the same length to keep the transmission time difference between different nets within an acceptable range. We take the motherboard as an example. There are hundreds of critical nets connecting the CPU to the memory, and there are many length matching rules to meet to maintain the correctness of the signals. The routing problem on the motherboard currently relies on manual methods. Although manual routing can achieve a 100% completion rate, it costs lots of time to fine-tune the lengths of the nets and may violate other design rules when adjusting the lengths. To shorten the time of manual adjustment, we propose a length matching algorithm for printed circuit boards (PCBs). Based on the manual routing result, the algorithm first calculates the tuning length of each net and then adjusts the net physically to solve the length matching problem. To control the distance between a net and obstacles, we use the geometric calculation method to calculate the distance directly to eliminate the error caused by placing the net and obstacles on the grid. The experimental results show that our algorithm can calculate the length of each net and adjust the nets in a few seconds with a success rate of 75% without violating the design rules.

1 Introduction --------------------------------- 1
1.1 Motivation --------------------------------- 1
1.2 Previous Work ------------------------------ 2
1.3 Our Contributions -------------------------- 4
1.4 Thesis Organization ------------------------ 4
2 Problem Formulation -------------------------- 5
2.1 Direction Constraint ----------------------- 5
2.2 Spacing Constraint ------------------------- 6
2.2.1 The Spacing of Net and Net --------------- 7
2.2.2 The Spacing of Net and Pin --------------- 8
2.2.3 The Spacing of Net and Via --------------- 10
2.3 Length-Matching Constraint ----------------- 10
2.4 Problem Description ------------------------ 13
3 Methodology ---------------------------------- 14
3.1 Overall Flow ------------------------------- 14
3.2 Tuning Length Calculation ------------------ 17
3.2.1 Length Bound Updating -------------------- 19
3.2.2 Tuning Length Updating ------------------- 21
3.3 Tuning Process ----------------------------- 23
3.3.1 U-Shape Recognition ---------------------- 26
3.3.2 Net Shortening --------------------------- 28
3.3.3 Net Lengthening -------------------------- 30
4 Experimental Results ------------------------- 35
4.1 Experiment Setup --------------------------- 35
4.2 Results ------------------------------------ 37
4.3 Effectiveness ------------------------------ 41
5 Conclusion ----------------------------------- 42
References ------------------------------------- 43

1. M. Ozdal and M. D. F. Wong, “Length-matching routing for high-speed printed circuit boards,” in International Conference on Computer Aided Design, pp. 394–400, 2003.
2. M. Mustafa Ozdal and M. D. F. Wong, “A length-matching routing algorithm for high-performance printed circuit boards,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 12, pp. 2784–2794, 2006.
3. M. Ozdal and M. D. F. Wong, “A provably good algorithm for high performance bus routing,” in International Conference on Computer Aided Design, pp. 830–837, 2004.
4. M. Ozdal and M. D. F. Wong, “Algorithmic study of single-layer bus routing for high-speed boards,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 3, pp. 490–503, 2006.
5. Y. Kubo, H. Miyashita, Y. Kajitani, and K. Tateishi, “Equidistance routing in high-speed vlsi layout design,” Integration, vol. 38, no. 3, pp. 439–449, 2005.
6. T. Yan and M. D. F. Wong, “Bsgroute: A length-matching router for general topology,” in International Conference on Computer-Aided Design, pp. 499–505, 2008.
7. T. Yan and M. D. F. Wong, “Bsgroute: A length-constrained routing scheme for general planar topology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 11, pp. 1679–1690, 2009.
8. J.T. Yan and Z.W. Chen, “Obstacle-aware length-matching bus routing,” in International Symposium on Physical Design, pp. 61–68, 2011.
9. Y. Kohira and A. Takahashi, “Cafe router: A fast connectivity aware multiple nets routing algorithm for routing grid with obstacles,” in Asia and South Pacific Design Automation Conference, pp. 281–286, 2010.
10. Y. Kohira and A. Takahashi, “Cafe router: A fast connectivity aware multiple nets routing algorithm for routing grid with obstacles,” IEICE transactions on fundamentals of electronics, communications and computer sciences, vol. 93, no. 12, pp. 2380–2388, 2010.
11. R. Zhang, T. Pan, L. Zhu, and T. Watanabe, “A length matching routing method for disordered pins in pcb design,” in Asia and South Pacific Design Automation Conference, pp. 402–407, 2015.
12. Y. Kohira, S. Suehiro, and A. Takahashi, “A fast longer path algorithm for routing grid with obstacles using biconnectivity based length upper bound,” in Asia and South Pacific Design Automation Conference, pp. 600–605, 2009.
13. T.H. Li, W.C. Chen, X.T. Cai, and T.C. Chen, “Escape routing of differential pairs considering length matching,” in Asia and South Pacific Design Automation Conference, pp. 139–144, 2012.
14. Y.J. Lee, H.M. Chen, and C.Y. Chin, “On simultaneous escape routing of length matching differential signalings,” in IEEE Electrical Design of Advanced Packaging Systems Symposium, pp. 177–180, 2013.
15. Boost C++ Libraries, 1.74.0 ed. https://www.boost.org/users/history/version_1_74_0.html.
16. Cadence Inc., Allegro PCB Editor, 16.6 ed. https://www.cadence.com/zh_TW/home/tools/pcb-design-and-analysis/pc-design-flows/allegro-whats-new/16-6-release.html.