絕熱量子通量參變器（AQFP）是一種超導邏輯，具有非常低的能量消耗。每個 AQFP 單元均由交流電源驅動，同時作為電源供給和時脈訊號。時脈訊號觸發資料訊號從一個時鐘相位轉移到下一時鐘相位，而同一相位中每個輸出的延遲必須相等。同時，訊號電流會隨著導線變長而衰減。當電線超過最大長度限制時，衰弱的電流會導致資料訊號錯誤。因此，需要另外插入緩衝器以同時滿足延遲同步和線長限制。這些插入的緩衝器使整體功耗增加，也增加了電路的總時脈延遲。在本文中，我們提出了 AQFP 佈局演算法架構： ASAP。此架構提供有效的擺放結果，從而大大減少了額外插入的緩衝器數量。ASAP 包括兩個主要步驟：1）使用分析法的全局佈局和 2）細部佈局，包括固定順序的拉格朗日鬆弛和單元平衡演算法。實驗結果證明了 ASAP 的有效性，並且與過去文獻相比可減少53％的緩衝器數量。

Adiabatic Quantum-Flux-Parametron (AQFP) is a superconducting logic with very low energy dissipation. Each AQFP cell is driven by AC-power to serve as both power supply and clock signal. The clock signals trigger the data flow from one clock phase to the next clock phase, and the delay for each output in the same phase has to be equal. At the same time, the signal current attenuates as the wire becomes longer. When a wire exceeds a maximum length, the weak current causes incorrect data. Thus, rows of buffers have
to be inserted as repeaters to satisfy both delay synchronization and wirelength constraint. These inserted buffers significantly increase the power consumption and also the total delay of AQFP circuits. In this thesis, we propose an analytical strategy for AQFP placement (ASAP) to provide effective placement results that greatly reduce the number of additional inserted buffers. ASAP includes two main characteristics: 1) a new wirelength function for analytical global placement and 2) detailed placement including fixed-order Lagrangian relaxation and cell balancing algorithm. Experimental results show the efficiency of ASAP
framework and a 53% reduction of buffers over the state-of-the-art method.

Acknowledgement i
Abstract ii
1 Introduction 1
2 Preliminaries 3
3 ASAP Framework 8
4 Experimental Results 19
5 Conclusion 23
References 24

[1] Y.-C. Chang, H. Li, O. Chen, Y. Wang, N. Yoshikawa, and T.-Y. Ho, “Asap: An analytical strategy for aqfp placement,” in proceedings of the 39th International Conference on Computer-Aided Design, ICCAD ’20, Association for Computing Machinery, 2020.
[2] T. Tanaka, C. L. Ayala, Q. Xu, R. Saito, and N. Yoshikawa, “Fabrication of adiabatic quantum-flux-parametron integrated circuits using an automatic placement tool based on genetic algorithms,” IEEE Transactions on Applied Superconductivity, vol. 29, no. 5, pp. 1–6, 2019.
[3] N. I. H. M. Mukhanov O., Yoshikawa N., “Josephson junctions for digital applications,” in Fundamentals and Frontiers of the Josephson Effect, p. 621, Springer, Cham, 2019.
[4] Y. Murai, C. L. Ayala, N. Takeuchi, Y. Yamanashi, and N. Yoshikawa, “Development and demonstration of routing and placement eda tools for large-scale adiabatic quantum-flux-parametron circuits,” IEEE Transactions on Applied Superconductivity, vol. 27, no. 6, pp. 1–9, 2017.
[5] Y. Lin, S. Dhar, W. Li, H. Ren, B. Khailany, and D. Z. Pan, “Dreamplace: Deep learning toolkit-enabled gpu acceleration for modern vlsi placement,” in 2019 56th ACM/IEEE Design Automation Conference (DAC), pp. 1–6, 2019.
[6] N. Takeuchi, Y. Yamanashi, and N. Yoshikawa, “Adiabatic quantum-flux-parametron cell library adopting minimalist design,” Journal of Applied Physics, vol. 117, p. 173912, 05 2015.
[7] C. Cheng, A. B. Kahng, I. Kang, and L. Wang, “Replace: Advancing solution quality and routability validation in global placement,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 9, pp. 1717–1730, 2019.
[8] M. Hsu, Y. Chang, and V. Balabanov, “Tsv-aware analytical placement for 3d ic designs,” in 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 664–669, 2011.
[9] B. Yu, X. Xu, J. Gao, Y. Lin, Z. Li, C. J. Alpert, and D. Z. Pan, “Methodology for standard cell compliance and detailed placement for triple patterning lithography,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 5, pp. 726–739, 2015.
[10] T. Taghavi, Z. Li, C. Alpert, G. Nam, A. Huber, and S. Ramji, “New placement prediction and mitigation techniques for local routing congestion,” in 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 621–624, 2010.
[11] Y. Lin, B. Yu, Y. Zou, Z. Li, C. Alpert, and D. Pan, “Stitch aware detailed placement for multiple e-beam lithography,” Integration, the VLSI Journal, vol. 58, pp. 47–54, 06 2017.
[12] M. Held, P.Wolfe, and H. P. Crowder, “Validation of subgradient optimization,” 1974.