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作者(中文):嚴心平
作者(外文):Yen, Hsin-Ping
論文名稱(中文):一個可以提供晶圓調度時間建議的彈性半導體製造系統模擬框架
論文名稱(外文):A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time Recommendation
指導教授(中文):王俊堯
指導教授(外文):Wang, Chun-Yao
口試委員(中文):張世杰
陳勇志
口試委員(外文):Chang, Shih-Chieh
Chen, Yung-Chih
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學號:108062556
出版年(民國):110
畢業學年度:109
語文別:英文
論文頁數:28
中文關鍵詞:集束型設備模擬器晶圓傳送系統
外文關鍵詞:cluster toolsimulationwafer transferring system
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半導體製程相當耗時,晶圓的周轉時間對製程工程師是非常有用的資訊。使用模擬器可以高效率地預測製程的表現,提供製程工程師有利的資訊。模擬晶圓製程的結果還可以提供系統工程師如何增進產能的訊息。在此論文中,我們提出了一個通用的晶圓製造系統模擬框架。這個框架可以適用於不同構造和模式的晶圓製造系統。我們還提出了一個可在模擬器上實現不同晶圓調度的方式。我們也針對晶圓批次調度提出了一個方法,提供工程師晶圓批次調度時間的建議。我們用 SystemC 與 C++ 語言實作了模擬器。實驗所用的晶圓批次資訊是來自於業界的真實數據。實驗結果顯示,就整體時間而言,模擬結果與真實製程數據的差異小於2%,這代表著模擬器有相當高的精準度。 實驗結果也顯示,相較真實製程數據,使用我們提出的調度方法可以達到較高產能,因此可以向系統工程師推薦調度時間點。
The semiconductor manufacturing process consists of multiple steps and is usually time-consuming. Information like the turnaround time of a certain batch of wafers can be very useful for manufacturing engineers. A simulation model of manufacturing process can help predict the performance of manufacturing process efficiently, which is very beneficial to the manufacturing engineers. The simulation result can also deliver messages to system engineers for achieving better throughput after adjustment. In this work, we propose a flexible simulation framework for a cluster tool, which is the system for wafer processing. This framework can be adapted with different cluster tool configurations and modes. We also propose two scheduling methods about the simulator, and a dispatching method, which provides dispatching time point recommendations. We implemented the simulator in C++ language with SystemC. The batch information used for the design of simulator was gathered from industrial data.
The experimental results show that there is only less than 2% difference between the simulation and the manufacturing data in terms of entire processing time, which indicates the high accuracy of the simulator.
The experimental results with the proposed dispatching method achieve a higher throughput compared to the manufacturing data such that the dispatching time points can be recommended to the system engineers.
中文摘要 i
Abstract ii
誌謝辭 iii
Contents iv
List of Tables vi
List of Figures vii
1 Introduction 1
2 Background 5
2.1 Cluster Tool Configuration . . . . . . . . . . . . . . . . . . . 5
2.2 Inputs/Outputs and Features of the Simulator . . . . . . . . . . 6
2.3 Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Proposed Framework 8
3.1 Module Construction . . . . . . . . . . . . . . . . . . . . . . 8
3.1.1 Load Port . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.2 Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.3 Robot Arm . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.4 Load Lock . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.5 Buffer Arm . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.6 Chamber . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Batch Dispatching . . . . . . . . . . . . . . . . . . . . . . . 16
4 Experimental Results 18
5 Conclusion 25
[1] Tung-He Chou, Yu-Chih Chang, Binglung Yu, Chun-Fu Chen, Yung-Tai Hung, Tuung Luoh, Ling-Wuu Yang, Tahone Yang, Kuang-Chao Chen, “Capacity Simulation by Cellular Automation in Endura Platform,” in Proc. e-Manufacturing and Design Collaboration Symposium, 2016.
[2] Henry L. Gantt, “A graphical daily balance in manufacture,” Transactions of the American Society of Mechanical Engineers, vol 24, pp. 1322–1336, 1903.
[3] Taehee Jeong, Deeksha Prakash Kankalale, Raymond Chau, Hyeran Jeon, “Going Deeper or Wider: Throughput Prediction for Cluster Tools with Machine Learning,” in Proc. International Conference on Big Data Computing, Applications and Technologies, 2019.
[4] Chihyun Jung and Tae-Eog Lee, “An Efficient Mixed Integer Programming Model Based on Timed Petri Nets for Diverse Complex Cluster Tool Scheduling Problems,” IEEE Transactions on Semiconductor Manufacturing, 2012, vol. 25, no. 2, pp. 186-199.
[5] Chihyun Jung and Tae-Eog Lee, “Cyclic Scheduling of Cluster Tools With Nonidentical Chamber Access Times Between Parallel Chambers,” IEEE Transactions on Semiconductor Manufacturing, 2012, vol. 25, no. 3, pp. 420-431.
[6] Dae-Kyu Kim, Tae-Eog Lee, and Hyun-Jung Kim, “Optimal Scheduling of Transient Cycles for Single-Armed Cluster Tools,” in Proc. International Conference on Automation Science and Engineering, 2013, pp. 874-879.
[7] Sung-Gil Ko, Tae-Sun Yu , and Tae-Eog Lee, “Scheduling Dual-Armed Cluster Tools for Concurrent Processing of Multiple Wafer Types With Identical Job Flows,” IEEE Transactions on Automation Science and Engineering, 2019, vol. 16, no. 3, pp. 1058-1070.
[8] Jun-Ho Lee, Hyun-Jung Kim, and Tae-Eog Lee, “Scheduling Cluster Tools for Concurrent Processing of Two Wafer Types,” IEEE Transactions on Automation Science and Engineering, 2014, vol. 11, no. 2, pp. 525-536.
[9] George H. Mealy, “A method for synthesizing sequential circuits,” Bell Labs Technical Journal, vol 34, pp.1045-1079, 1955.
[10] Edward F. Moore, “Gedanken-Experiments on Sequential Machines,” Automata studies, pp. 129–153, 1956.
[11] David A. Nehme and Neal G. Pierce, “Evaluating the throughput of cluster tools using event-graph simulations,” in Proc. Advanced Semiconductor Manufacturing Conference and Workshop (ASMC), 1994, pp. 189–192.
[12] Sang C. Park, Euikoog Ahn, Yongho Chung, Ka-ram Yang, Byung H. Kim,
Jeong C. Seo, “Fab Simulation with Recipe Arrangement if Tools,” in Proc.
Winter Simulations Conference (WSC), 2013, pp. 3840-3849.
[13] Paht Te Quek, Boon Ping Gan , Song Lian Tan, Chan Lai Peng, Bart vd Heijden, “Analysis of the front-end wet strip efficiency performance for productivity,” in Proc. International Symposium on Semiconductor Manufacturing, 2007, pp. 1–4.
[14] Hiroe Watanabe, “Development of Wafer Transfer Simulator Based on Cellular Automata,” IEEE Transactions on Semiconductor Manufacturing, 2015, vol. 28, no. 3, pp. 283-288.
[15] Uno Wikborg and Tae-Eog Lee, “A Petri Net Method for Schedulability and Scheduling Problems in Single-Arm Cluster Tools With Wafer Residency Time Constraints,” IEEE Transactions on Semiconductor Manufacturing, 2008, vol. 21, no. 2, pp. 224-237.
[16] Uno Wikborg and Tae-Eog Lee, “Noncyclic Scheduling for Timed DiscreteEvent Systems With Application to Single-Armed Cluster Tools Using ParetoOptimal Optimization,” in Proc. International Conference on Automation Science and Engineering, 2013, vol. 10, no. 3, pp. 699-710.
[17] Xiuhong Zheng, Jingtao Hu, Haibin Yu, “Research on a simulation platform assisting analysis of the cluster tool,” in Proc. International Conference on Computer Research and Development, pp. 249-253, 2011.
[18] Wlodek M. Zuberek, “Cluster Tools With Chamber Revisiting—Modeling and Analysis Using Timed Petri Nets,” IEEE Transactions on Semiconductor Manufacturing, 2004, vol. 17, no. 3, pp. 333-344.
[19] Plotly Technologies Inc., “Collaborative data science,” Available: https://plot.ly.
 
 
 
 
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