在以非常高速傳輸數據的現代數位通訊系統中，錯誤更正通常是必不可少的。最近發布的 IEEE Std 802.3bs 要求驚人的 200Gbps 甚至 400Gbps 傳輸速度，使用里德-所羅門碼 (RS-Code) 進行錯誤更正，以保護傳輸過程中數據的正確與完整性。支援如此高速傳輸的 RS-Codec 需要複雜的硬體實現。儘管已經有大量關於實現高傳輸 RS-Codec 的著作，但尚未系統地利用傳輸速度驅動的面積和功率優化。在這項論文中，我們提供了應對這一挑戰的見解。我們的貢獻在兩個方面特別獨特。首先，我們使用 RS(544, 514) 協定開發來滿足 IEEE Std 802.3bs 的參數化編解碼器的 VLSI 架構，其中可以通過設置一些“參數”來按需提高傳輸量。其次，我們開發了基於上述架構的 RS-Codec 編譯器，因此可以在短短幾分鐘內輕鬆生成滿足目標傳輸速度的面積和功耗高效的 RS-Codec 設計。將展示使用 28nm 和 90nm CMOS 製程的實驗結果，以證明其有效性。

Error Correction is often indispensable in a modern digital communication system that transmits data at a very high speed. Recently published IEEE Std 802.3bs requiring an astounding throughput of 200Gbps or even 400Gbps uses Reed-Solomon Code (RS-Code) for Error Correction to protect the integrity of the data during the transmission. An RS-Codec supporting such a high throughput demands sophisticated hardware implementation. Even though there have been numerous works on the implementation of high-throughput RS-Codec, the throughput-driven area and power optimization has not been exploited systematically. In this work, we provide insight on meeting this challenge. Our contributions are particularly unique in two aspects. First, we developed the VLSI architecture of parameterized Codec satisfying IEEE Std 802.3bs using RS(544, 514), in which the throughput can be boosted on demand by setting some “configuration”. Second, we developed an RS-Codec compiler based on the above architecture, so that one can easily produce an area and power efficient RS-Codec design satisfying a target throughput in just minutes. Experimental results using 28nm and 90nm CMOS processes will be presented to demonstrate its effectiveness.

摘要 i
Abstract ii
致謝 iii
Content iv
List of Figure vi
List of Tables viii
Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Thesis Organization 4
Chapter 2 Preliminaries 5
2.1 Galois Field 5
2.2 Reed-Solomon Code for IEEE Std 802.3bs 7
2.3 Encoding of Reed-Solomon Codes 9
2.4 Decoding of Reed-Solomon Codes 11
Chapter 3 Primitive RS Codec Design 14
3.1 Efficient Implementation of GF Multiplier 14
3.2 Primitive RS-Encoder 16
3.3 Primitive RS-Decoder 18
Chapter 4 Proposed High-Performance RS Codec Design 30
4.1 Configuration 30
4.2 Parallel Encoder 31
4.3 Parallel Decoder 34
4.4 Compiler for RS-Codec 40
Chapter 5 Experimental Results & Comparison 42
5.1 RS Codec for IEEE Std 802.3bs 42
5.2 Verification 46
5.3 Comparison 48
5.4 RS (544, 514) Codec Compiler 50
5.5 Layout of RS Codec TP (Ch: 12, SIP: 16) 56
Chapter 6 Conclusion & Future Work 58
6.1 Conclusion 58
6.2 Future Work 58
References 60

[1] IEEE Standard 802.3bs-2017.
[2] “Forward Error Correction for Submarine Systems,” Telecommunication Standardization Section, International Telecom. Union, ITU-T Recommendation G.975, Oct., 2000.
[3] G. Perrone, J. Valls, V. Torres and F. M. García-Herrero, "High-Throughput One-Channel RS(255,239) Decoder," 21st Euromicro Conf. on Digital System Design (DSD), pp. 110-114, 2018.
[4] W. Ji, W. Zhang, X. Peng, and Z. Liang, “16-Channel Two-Parallel Reed-Solomon Based Forward Error Correction Architecture for Optical Communications,” Proc. of IEEE Int’l Conf. on Digital Signal Processing (DSP), pp. 239–243. July 2015.
[5] J. Park, K. Lee, C. Choi, and H. Lee, "High-Speed Low-Complexity Reed-Solomon Decoder using Pipelined Berlekamp-Massey Algorithm," Proc. of Int’l SoC Design Conf. (ISOCC), pp. 452-455, 2009.
[6] H. Lee, C. -S. Choi, J. Shin and J.S. Ko, "100-Gb/s Three-Parallel Reed-Solomon Based Forward Error Correction Architecture for Optical Communications," Proc. of Int’l SoC Design Conf. (ISOCC), pp. I-265-I-268, 2008.
[7] J. Park, J. Yeon, S. Yang, and H. Lee, "An Ultra High-Speed Time-Multiplexing Reed-Solomon-Based FEC Architecture," Proc. of Int’l SoC Design Conf. (ISOCC), pp. 451-454, 2012.
[8] E. R. Berlekamp, “Algebraic Coding Theory”, McGraw-Hill, 1968.
[9] R. E. Blahut, “Theory and Practice of Error-Control Codes”, Addison-Wesley, 1983.
[10] H. Lee, "High-Speed VLSI Architecture for Parallel Reed-Solomon Decoder," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 2, pp. 288-294, April 2003.
[11] D. V. Sarwate and N. R. Shanbhag, “High-Speed Architecture for Reed-Solomon Decoders,” IEEE Trans. on VLSI Systems, Vol. 9, No. 5, pp. 641-655, Oct., 2001.
[12] R. T. Chien, “Cyclic Decoding Procedures for Bose-Chaudhuri-Hocquenghem Codes,” IEEE Transactions on Information Theory, pp. 357-363, October 1964.
[13] G. D. Forney, “On Decoding BCH Codes,” IEEE Transactions on Information Theory, pp. 549-557, October 1965.
[14] H. Lee, M.-L. Yu, and L. Song, "VLSI Design of Reed-Solomon Decoder Architectures," Proc. of Int’l Symp. on Circuits and Systems (ISCAS), pp. 705-708 Vol. 5, 2000.
[15] Y. Lu and M. Shieh, "Efficient Architecture for Reed-Solomon Decoder," Proc. of VLSI Design, Automation and Test, pp. 1-4, 2012.
[16] Y. Wu, "New Scalable Decoder Architectures for Reed–Solomon Codes," in IEEE Transactions on Communications, Vol. 63, No. 8, pp. 2741-2761, Aug. 2015.
[17] T.-B. Pei, and C. Zukowski, “High-Speed Parallel CRC Circuits in VLSI,” IEEE Trans. on Communication, Vol. 40, No. 4, pp. 653-657, Apr. 1992.
[18] M. Ayinala and K. K. Parhi, “High-Speed Parallel Architectures for Linear Feedback Shift Registers,” IEEE Trans. on Signal Process, Vol. 59, No. 9, pp. 4459-4469, Sept. 2011.
[19] J. Jung, et. al., “Efficient Parallel Architecture for Linear Feedback Shift Registers,” IEEE Trans. on Circuits and System, Part II, Vol. 62, No. 11, pp. 1068-1072, Nov. 2015.
[20] X. Zhang, "High-Speed and Low-Complexity Parallel Long BCH Encoder," Proc. of IEEE Int’l Symp. on Circuits and Systems (ISCAS), pp. 1-5, 2020.
[21] S. Lee, C.-S. Choi, and H. Lee, “Two-Parallel Reed-Solomon Based FEC Architecture for Optical communications,” IEICE Electronics Express, Vol. 5, No. 10, pp. 374-380, 2008.