隨著半導體產業的進步，通訊世界也蓬勃發展，如4G通訊技術使得在3G時代無法實現的變成可能。聲音處理方面大家為了講求更高的音質，在醫療中對生理訊號量測更精準的判別微小變化，又或者對於微小的溫度變化進行監控，類比數位轉換器是一個無法被取代掉的部份。本論文設計一個輸入頻寬為20kHz，超取樣率256，取樣頻率10MHz的二階前饋三角積分類比數位轉換器，主要應用於溫度感測，使用交換式電容(Switch Capacitor)實現離散時間系統。整體的架構主要包括放大器(OP)、開關(switch)、比較器(Comparator)等等。經由探討並解決各種非理想效應如放大器有限增益(Gain) 、時脈饋穿(Clock Feedthrough) 、雜訊(noise)等等進行電路上的規格設計。
在經由速度與解析度的取捨，下本論文以TSMC 65nm CMOS 1P9M實現，供應電壓為1.2 V，輸入頻寬為20kHz，超取樣率256，取樣頻率10MHz，得到有效位元數(ENOB)為15.116bits，功率消耗為3.234mW

With the development of the semiconductor industry, the communication world is also booming, 4G technology provide high transmission speed for signal. ADC are an irreplaceable part of the system and it can effectively convert analog signals into digital signals. There are different types of ADCs. This paper designs a second-order feed-forward delta-sigma analog-to-digital converter with a signal bandwidth of 20kHz, an oversampling ratio(OSR) is 256, and a maximum frequency of 10MHz. It is mainly used in temperature sensing and uses switching capacitors (switched capacitors) to implement discrete-time systems. The overall architecture mainly includes OP amplifier, switch, comparator and so on. Touch the switch and solve various non-ideal effects such as gain, clock feedthrough, noise, etc., to design the circuit specifications.
In terms of speed and resolution, this paper is implemented with TSMC 65nm CMOS 1P9M, the supply voltage is 1.2V, the signal bandwidth is 20kHz, oversampling ratio(OSR) is 256, the high frequency is 10MHz, signal to noise ratio SNR>92dB, and ENOB is 15.116 bits. The power consumption is 3.234mW

中文摘要 i
Abstract(英文摘要) ii
目錄 iii
表目錄 ix
第一章 序論 1
1.1 研究動機 1
1.2 論文章節組織 1
第二章 研究背景與相關研究介紹 3
2.1 類比數位轉換器參數 3
2.1.1 基本名詞 3
2.1.1.a 解析度(Resolution) 3
2.1.1.b 取樣率(Sampling Rate) 4
2.1.1.c 最小解析度(Least Signification Bit) 4
2.1.1.d 量化誤差(Quantization Error) 4
2.1.2 動態效能 4
2.1.2.a 訊號雜訊比(signal-to-noise-ratio , SNR) 4
2.1.2.b 訊號雜訊諧波失真比(signal-to-noise and distortion
ratio,SNDR) 4
2.1.2.c 有效位元數(Effective Nunber of Bits , ENOB) 5
2.1.2.d 無雜訊動態範圍(spurious-free dynamic range , SFDR) 5
2.1.2.e 動態範圍(Dynamic Range) 5
2.1.2.f 總諧波失真(total harmonic distortion , THD) 6
2.2 類比數位轉換器比較：6
2.3 三角積分類比數位轉換器介紹 8
2.3.1 基本結構 8
2.3.2 離散時間與連續時間(DT/CT) 11
2.4 取樣定理 15
2.5 量化定理 16
2.6 超取樣(Oversampling) 20
2.7 雜訊整形(Noise Shaping) 23
2.8 穩定度 31
2.8.1 李氏準則(Lee’s criterion) 32
2.8.2 根軌跡(Root locus) 32
2.8.3 頻帶外增益(out-of-band gain，OBG) 34
第三章 系統層面規畫與模擬 35
3.1 系統規格 35
3.2 調變器架構介紹 36
3.2.1 二階CIFB(Chain of integrators with distributed feeback) 36
3.2.2 二階CIFF(Chain of integrators with feed-forward) 37
3.3 調變器架構選取 38
3.4 三角積分調變器系統之線性模型 38
3.5 三角積分調變器之交換電容積分器 42
3.6 雜訊分析 44
3.6.1 取樣電路之雜訊 44
3.6.2 積分器電路之雜訊分析 45
3.6.3 三角積分調變器中的雜訊分析 48
第四章 子電路設計與模擬結果 52
4.1 開關(Switch)設計 52
4.1.1 時脈饋入(Clock Feedthrough) 55
4.1.2 通道電荷注入(Channel Charge injection)效應 56
4.1.3 虛擬開關(Dummy Switch) 58
4.1.4 下板取樣(Bottom Plate Sampling) 59
4.2 運算放大器設計 59
4.3 交換式電容積分器設計 67
4.4 比較器設計 70
4.5 時脈產生器設計 73
4.6 加法器設計 75
4.7 一位元回授DAC設計 76
4.8 完整電路模擬結果： 77
第五章 結論與未來工作 80
5.1 結論 80
5.2 未來工作 80
參考文獻 81

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