隨著科技的進步，越來越多電子產品的誕生，積體電路有著非常重要的地位，而其中有許許多多電子產品都仰賴類比數位轉換器，類比數位轉換器是電子產品與大自然之間的橋樑。

隨著數位訊號處理越來越發達，現在的訊號處理皆以數位電路的方式，也多虧了數位訊號處理的可靠度以及速度，人人類社會得以進步如此之快速，但是大自然的訊號都以類比的形式存在，這時就得依賴類比數位轉換器來使系統能順利運作。

現今有許多不同類型的類比數位轉換器被提出以應付不同需求，本論文實現了一個二階被動雜訊整形之連續漸進式類比數位轉換器，在每秒八千萬次取樣的速度下，其二階雜訊整形使用了8DAC，來達到雜訊整形的效果，希望能在低公耗的情況下達到不錯的雜訊失真比，這個 9 位元連續漸進式類比數位轉換器利用台積電 65 奈米的 CMOS 製程來設計，操作電壓為 1.2V。

As technology advances, the birth of more and more electronic products, integrated circuit has a very important position, of which there are many electronic products rely on analog to digital converter. Analog-to-digital converters are the bridge between electronic products and nature.

As digital signal processing has become more and more advanced, current signal processing is done in the form of digital circuits. Thanks to the reliability and speed of digital signal processing, human society has progressed so fast, but the signals of nature are analogous. You have to rely on analog-to-digital converters to make the system operate.
Nowadays, many different types of analog-to-digital converters have been proposed to meet different needs. This paper implements a SAR analog-to-digital converter with second-order passive noise shaping.
At a Sampling rate of 80MHz, its second-order Noise shaping uses 8DAC to achieve the effect of noise shaping.
We hope to achieve a good SNDR with low power consumption. This 9-bit SAR analog-to-digital converter uses TSMC’s 65nm CMOS Designed, the operating voltage is 1.2V.

目錄

中文摘要 I
Abstract(英文摘要) II
目錄 III
圖目錄 VI
第一章 簡介 1
1.1 研究動機(Motivation) 1
1.2 論文章節組織 2
第二章 研究背景以及相關研究介紹 3
2.1 奈奎斯特取樣理論簡介 4
2.1.1 專有名詞 4
2.1.1.a 解析度(Resolution) 5
2.1.1.b 最小解析度(Least Significant Bit) 5
2.1.1.c 取樣率(Sampling Rate) 5
2.1.1.d 量化誤差(Quantization Error) 5
2.1.2 靜態特性 7
2.1.2.a 偏差(Offset) 7
2.1.2.b 增益誤差(Gain Error) 7
2.1.2.c 差動非線性度(Differential Nonlinearity) 8
2.1.2.d 積分非線性度(Integral Nonlinearity) 9
2.1.2.e 遺失碼(Missing Codes) 9
2.1.3 動態特性 10
2.1.3.a 訊號與雜訊比(Signal-to-Noise Ratio) 10
2.1.3.b 訊號與雜訊諧波比(Signal-to-Noise and Distortion Ratio) 10
2.1.3.c 有效位元數(Effective Number of Bits) 10
2.1.3.d 無雜訊動態範圍(Spurious Free Dynamic Range) 10
2.1.3.e 動態範圍(Dynamic Range) 11
2.1.3.f 總諧波失真(Total Harmonic Distortion 11
2.2 連續漸進式類比數位轉換器(SAR ADC) 11
2.2.1 SAR ADC簡介及架構圖 11
2.2.2 電荷重新分佈SAR ADC(Charge Redistribution SAR ADC) 12
2.3 電容切換演算法. 14
2.3.1 傳統式電容切換演算法(Conventional switching algorithm) 15
2.3.2 單調性電容切換演算法(Monotonic switching algorithm) 16
2.3.3 電容拆半切換演算法 18
2.3.4 單向電容切換演算法 19


Ⅲ



2.4 帶冗餘位演算法 20
2.5 超取樣(Over Sampling)與雜訊整形(Noise Shaping) 21
2.5.1 奈奎斯特取樣轉換器與超取樣轉換器性能之比較 21
2.5.2 超取樣(Over sampling) 22
2.5.3 雜訊整形(Noise Shaping) 23
第三章 具雜訊整形之連續漸進式類比數位轉換器之設計 24
3.1 架構原理 24
3.2 連續漸進式類比數位轉換器(SAR ADC)子電路介紹 29
3.2.1 取樣及保持電路(Sample and Hold) 29
3.2.1.a 電路原理 29
3.2.1.b 設計考量 30
3.2.1.c 電路實作 32
3.2.1.d 模擬結果 34
3.2.2 比較器(Comparator) 35
3.2.2.a 電路原理 36
3.2.2.b 設計考量 37
3.2.2.c 電路實作 39
3.2.3 電容矩陣(Capacitor Array) 40
3.2.4 連續漸進式邏輯電路(SAR Logic) 41
3.2.4.a 內部時序邏輯(CLK generator) 41
3.2.4.b 非重疊時脈產生器(No-overlap CLK) 43
3.2.4.c 控制邏輯(Control Logic) 44
3.2.4.d 電容陣列緩衝器 45
第四章 模擬結果 46

第五章 參考文獻 47

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