線上速度分級設計是一種可以支持晶片上測出待測電路最快操作速度的一種技術。在以往沒有適當的時脈產生方法下，傳統的線上速度分級設計是沒辦法容忍待測電路在實際晶片中的製程變異，進而導致沒辦法量測到真正準確的最快操作速度之可能性。在本論文中，我們提出了以待測電路自身估計的關鍵路徑延遲為中心，去擴展測試時脈週期範圍的動態時脈產生設置方法。藉由此方法，測試時脈週期餘量將會十分平均地擴展在待測電路自身估計的關鍵路徑延遲的兩側，使得測試時脈週期有更多彈性去涵蓋待測電路的製程變異影響。除此之外，與之前線上速度分級設計的時脈產生方法相比，我們提出的方法在同樣沒有待測電路的基礎下，實際布局面積可以有43.4%的降幅，同時維持著寬頻的測試時脈週期範圍，從[0.8ns, 25ns], 也就是[40MHz, 1.25GHz]，以及步幅的解析度可達到待測電路估計的關鍵路徑延遲之1%。
同時我們也開發了在門級模擬下便可使用的用於根據每個不同的基準電路自動找尋其適合的隨機測試輸入組數的自我收斂方法。應用本方法在我們所找尋的多組基準電路測試下，其隨機測試輸入組數和一般可信的隨意輸入組數，至少幾千筆組數相比，降幅可達數倍甚至十幾倍之多。最後，由於提出的時脈產生方法同樣也可達到非常細微的步輻解析度，因此利用本文內所提出的模擬置入老化故障的方法，我們的線上速度分級設計也可達到非常細緻的老化故障偵測，並且找出有早夭傾向的待測電路。

Built-In Speed Grading (BISG) is a technique that enables to On-Chip determine the maximum operating speed (Fmax¬) of the circuit under test (CUT). Without the proper clock generation scheme, the conventional BISG cannot tolerate the process variation of CUT in real silicon and therefore causing the possibility of failure to gauge the accurate Fmax of CUT. This thesis proposes a dynamic clock generation settings scheme, which is a CUT-specific test clock period range, centered around the estimated critical path delay of CUT. With the balanced test clock period margin for the high-speed target period, it makes more flexibility to cope with the process variation of CUT. Moreover, compared to the previous clock generation scheme for BISG, the total layout area without the CUT can be reduced by 43.4%, while achieving the wide-range test clock period range over [0.8ns, 25ns], i.e., [40MHz, 1.25GHz] and the step resolution is 1% of the estimated critical path delay of CUT.
Meanwhile, we develop a Self-Convergence method for automatically finding the suitable total number of random test patterns for each benchmark in gate-level simulation. By applying this method to our set of benchmarks, the total number of test patterns can not only be decided but also reduced more than ten times. Last but not the least, since our clock generation scheme also reaches the fine granularity of step resolution, we proposed a procedure of mimicked aging fault injection to demonstrate the aging effect detection and identify infant mortality by our BISG.

Abstract ii
摘要 iii
Content iv
List of Figures vi
List of Tables vii
Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Thesis Organization 6
Chapter 2 Preliminaries 7
2.1 Previous Clock Generation Architecture 7
2.2 Built-In Self-Test (BIST) Session for At-Speed Test 8
2.3 Flow Chart of Previous Work 10
2.4 Problem Statement of Previous Work 11
Chapter 3 Proposed Clock Generation scheme and Validation 13
3.1 Specification of Clock Generation Scheme 13
3.2 Proposed Built-In Speed Grading Flow and Architecture 17
3.3 Self-Convergence of the total number of random test patterns 22
3.3.1 Primitive Self-Convergence 22
3.3.2 Issues of Primitive Self-Convergence 25
3.3.3 The improved proposed Self-Convergence method 26
3.4 Experimental results 29
Chapter 4 Aging and Infant Mortality Detection 33
4.1 Proposed mimicked aging fault injection 33
4.2 Experimental results 35
Chapter 5 Conclusion 41
References 42

[1] A. Raychowdhury, S. Ghosh, and K. Roy, “A novel on-chip delay measurement hardware for efficient speed-binning,” Proc. 11th IEEE Int. On-Line Test. Symp., pp. 287–292, 2005.
[2] M.-C. Tsai, C.-H. Cheng, and C.-M. Yang, “An all-digital high-precision built-in delay time measurement circuit,” Proc. 26th IEEE VLSI Test Symp., pp. 249–254, 2008.
[3] X. Wang, M. Tehranipoor, S. George, D. Tran, and L. Winemberg, “Design and analysis of a delay sensor applicable to process/environmental variations and aging measurements,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 20, no. 8, pp. 1405–1418, 2012.
[4] D. Zhang and X. Wang, "An on-chip binning sensor for low-cost and accurate speed binning," 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM), pp. 151-155, 2017.
[5] H.-J. Hsu, C.-C. Tu, and S.-Y. Huang, “Built-In Speed Grading with a Process-Tolerant ADPLL,” Proc. Asian Test Symp. (ATS), pp. 384–389, 2007.
[6] C.-I. Chung, J.-S. Jhou, C.-H. Cheng and S.-Y. Li, “Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test,” Proc. Asian Test Symp. (ATS), pp. 163-168, 2009.
[7] S.-Y. Huang, T.-H. Huang, K.-H. Tsai and W.-T. Cheng, "A wide-range clock signal generation scheme for speed grading of a logic core," International Conference on High Performance Computing & Simulation (HPCS), pp. 125-129, 2016.
[8] Q. Shi, M. Tehranipoor, X. Wang, and L. Winemberg, “On-chip sensor selection for effective speed-binning,” Proc. 57th IEEE Int. Midwest Symp. Circuits Syst., pp. 1073–1076, 2014.
[9] S.-P. Mu, M. C.-T. Chao, S.-H. Chen and Y.-M. Wang, “Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 24, no. 5, pp. 1675-1687, 2016.
[10] M. Sadi, S. Kannan, L. Winemberg and M. Tehranipoor, “SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, no. 5, pp. 842-854, 2017.
[11] K. A. Brand, S. Mitra, E. Volkerink and E. J. McCluskey, "Speed clustering of integrated circuits," Proc. of IEEE Int'l Test Conf. (ITC), pp. 1128-1137, 2004.
[12] C.-W. Tzeng, S.-Y. Huang, P.-Y. Chao, and R.-T. Ding, “Parameterized All-Digital PLL Architecture and Its Compiler to Support Easy Process Migration,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 22, No. 3, pp. 621-630, 2014.
[13] C.-L. Tsai and S.-Y. Huang, "Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning," Proc. of IEEE Int'l Test Conf. (ITC), pp. 1-8, Sept. 2022.
[14] G.-H. Lian, W.-Y. Chen, and S.-Y. Huang, "Cloud-Based Online Ageing Monitoring for IoT Devices," IEEE Access, vol. 7, pp. 135964-135971, 2019.
[15] X. Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson, and N. Tamarapalli, “High-Frequency, At-Speed Scan Testing,” IEEE Design Test Computers, Vol. 20, No. 5, pp. 17–25, 2003.
[16] N. Ahmed, M. Tehranipoor, and C. P. Ravikumar, "Enhanced Launch-off-Capture Transition Fault Testing", Proc. of IEEE Int'l Test Conf. (ITC), pp. 246-255, 2005.
[17] J. Lee and E. J. McCluskey, “Failing Frequency Signature Analysis,” Proc. of IEEE Int'l Test Conf. (ITC), pp. 1-8, 2008.
[18] H. Yan and A. D. Singh, “Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Result from Neighboring die,” Proc. of IEEE Int'l Test Conf. (ITC), pp. 105-111, 2003.
[19] H. Yan and A. D. Singh, “Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Result from Neighboring die,” Proc. of IEEE Int'l Test Conf. (ITC), pp. 105-111, 2003.
[20] “EDA cloud Cell-based Flow” Taiwan Semiconductor Research Institute, TSRI, Taiwan.