人們所生活的環境為類比訊號的世界，然而隨著科技發展的進步，不論是在資料儲存、資訊運算或是訊號處理等等，電腦所提供的數位世界已經成為不可或缺的一環，為了使類比世界能與數位世界產生連結，因此類比數位轉換器成為了十分重要的存在。
本論文提出一個每秒8000萬次取樣12位元帶冗餘位連續漸進式類比數位轉換器，使用台積電65奈米製程來設計，供應電壓為1.2V，輸入訊號為39.62890625MHz接近奈奎斯特頻率的模擬之下，DNL為+0.253/-0.248 LSB，INL為+0.118/-0.183 LSB，無雜訊動態範圍(SFDR)為79.85 dB，訊號失真比(SNDR)為72.25 dB，有效位元數(ENOB)為11.71 bit，平均消耗功率為5.475mW。

The environment people live in is a world of analog signals. However, with the advancement of technology, the digital world provided by computers has become an indispensable part, whether in data storage, information computing or signal processing. The analog world can be connected with the digital world, so the analog-to-digital converter has become a very important existence.
A 80MS/s 12-bit Sucessive-Approximation Analog-to-Digital Converter With Redundancy is implemented in a TSMC 65 nm CMOS technology. The supply voltage is 1.2 V. With the input frequency 69.453 MHz,near the Nyquist frequency,The DNL is +0.253/-0.248 LSB and the INL is +0.118/-0.183 LSB. The SFDR is 79.85dB,the SNDR is 72.25dB and the effective number of bits (ENOB) is11.71 bits.The average power consumption in this work is 5.475 mW .

摘要 ii
Abstract iii
目錄 iv
圖目錄 x
表目錄 xv
第一章 緒論 1
1.1 研究動機 1
1.2 論文章節組織 1
第二章 研究背景以及相關研究介紹 3
2.1 類比數位轉換器參數 3
2.1.1 專有名詞 3
2.1.1.a 取樣率(Sampling Rate) 3
2.1.1.b 解析度(Resolution) 3
2.1.1.c 最小解析度(Least Signification Bit , LSB) 4
2.1.1.d 量化誤差(Quantization Error) 4
2.1.2 靜態特性 6
2.1.2.a 偏移誤差(Offset) 6
2.1.2.b 增益誤差(Gain Error) 6
2.1.2.c 差動非線性度(Differential Nonlinearity) 7
2.1.2.d 積分非線性度(Integral Nonlinearity) 8
2.1.2.e 遺失碼(Missing Code) 9
2.1.3 動態特性 10
2.1.3.a 訊號與雜訊比(Signal-to-Noise Ratio , SNR) 10
2.1.3.b 訊號與雜訊諧波比(Signal-to Noise and Distortion Ratio , SNDR) 11
2.1.3.c 無雜訊動態範圍(Spurious Free Dynamic Range , SFDR) 11
2.1.3.d 總諧波失真(Total Harmonic Distortion , THD) 11
2.1.3.e 有效位元數(Effective Number Of Bits , ENOB) 11
2.1.3.f 動態範圍(Dynamic Range) 12
2.2 類比數位轉換器之類型 12
2.2.1 奈奎斯特取樣定理(Nyquist Sampling Theorem) 12
2.2.2 超取樣(Oversampling) 13
2.2.3 管線式類比數位轉換器(Pipeline ADC) 14
2.2.4 快閃式類比數位轉換器(Flash ADC) 15
2.2.5 連續漸進式類比數位轉換器(Sucessive-Approximation Register ADC , SAR ADC) 16
第三章 連續漸進式類比數位轉換器之原理與操作模式 18
3.1 數位類比轉換器(Digital-to-Analog Converter , DAC) 18
3.1.1 電阻式DAC(Resistor DAC) 18
3.1.2 電流引導式DAC(Current Steering DAC) 19
3.1.3 電容切換式DAC(Switched-Capacitor DAC) 20
3.2 電容切換演算法 24
3.2.1 電容切換能量 24
3.2.2 傳統式電容切換演算法(Convential Switching Algorithm) 25
3.2.3 電容拆半式切換演算法(Split-Capacitor Switching Algorithm) 27
3.2.4 單調性電容切換演算法(Monotonic Switching Algorithm) 29
3.2.5 共模切換演算法(Merged-Capacitor Switching Algorithm) 30
3.2.6 雙向電容切換演算法(Bi-Direction Switching Algorithm) 32
3.3 單端(Single)與雙端(Differential)架構 34
3.4 同步(Synchronous)與非同步(Asynchronous)時脈 34
3.4.1 同步時脈 34
3.4.2 非同步時脈 35
3.5 冗餘演算法(Redundancy Algorithm) 36
3.5.1 二進位搜索演算法(Binary Search Algorithm) 36
3.5.2 非二進位搜索演算法(Non-Binary Search Algorithm) 37
3.5.3 帶錯誤補償的二進位搜索演算法(Binary Search With Error Compensation Algorithm) 37
3.5.4 二進位權重重組演算法(Binary-Scaled Recombination Weighting Algorithm) 38
3.5.5 冗餘範圍(Redundancy Range) 39
第四章 連續漸進式類比數位轉換器之設計 41
4.1 連續漸進式類比數位轉換器之架構 41
4.2 取樣保持電路(Sample and Hold) 41
4.2.1 電路功能與原理 41
4.2.2 設計考量 42
4.2.2.a 線性度(Linearity) 42
4.2.2.b 頻寬(Bandwidth) 45
4.2.2.c 精確度(Accurancy) 45
4.2.3 電路實作 47
4.2.4 模擬結果 49
4.3 比較器(Comparator) 51
4.3.1 電路功能與原理 51
4.3.2 比較器種類 51
4.3.2.a 靜態比較器(Static Comparator) 51
4.3.2.b Strong Arm動態比較器(Strong Arm Dynamic Comparator) 52
4.3.2.c 雙尾動態比較器(Double-Tail Dynamic Comparator) 53
4.3.2.d 兩級動態比較器(Two-Stage Dynamic Comparator) 54
4.3.3 設計考量 55
4.3.3.a 速度(Speed) 55
4.3.3.b 偏移誤差(Offset Error) 55
4.3.3.c 回饋雜訊(Kick-Back Noise) 55
4.3.4 電路實作 56
4.3.5 模擬結果 57
4.4 電容矩陣 59
4.4.1 電容種類 59
4.4.1.a MOS電容(Metal Oxide Semiconductor Capacitor) 59
4.4.1.b MIM電容(Metal Insulator Metal Capacitor) 59
4.4.1.c MOM電容(Metal Oxide Metal Capacitor) 60
4.4.2 電容權重分配 61
4.5 數位邏輯電路 61
4.5.1 時脈產生電路 62
4.5.2 邏輯控制電路 63
4.5.3 數位錯誤校正電路 64
4.6 80MS/s 12-bit帶冗餘位SAR ADC之模擬結果 65
第五章 結論與未來研究目標 70
參考文獻 71

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