在產生高頻信號的IC中鎖相迴路是必不可少的。對於安全關鍵的應用，容錯(Fault and Soft-Error Tolerance)方法是我們一直追求的特性。但是要如何使鎖相迴路有容忍錯誤的能力還是一項挑戰。在本論文中，我們提出一個使用三重模塊冗餘(Triple Module Redundancy)技術之容錯型鎖相迴路電路設計去應對這個問題。在本論文中，模擬的結果顯示單純的使用三重模塊冗餘技術之鎖相迴路無法正常運作，除非我們能解決訊號同步的問題，因此我們提出一個在三重模塊冗餘投票前的同步技術完成草率的容錯型鎖相迴路電路設計。除此之外，我們藉由細心擺放相位比較器並改用感官放大器(Sense Amplifier)來優化電路表現及減少面積。通過細心擺放，訊號抖動量的峰值差可以由使用草率容錯型鎖相迴路電路的25皮秒降到12皮秒，而通過使用感官放大器取代原本的相位比較器，相比原始的鎖相迴路電路的面積倍率能從687%縮減到675%
我們獨特的貢獻是使用”投票前同步技術”來達到容錯能力同時也維持訊號抖動量的穩定。最後我們使用90nmCMOS製程的後端模擬來展示我們的鎖相迴路可以容忍來自在線的錯誤還有來自外部高能輻射帶來的軟錯誤並且不會有可觀的抖動性能損失。

A Phase-Locked Loop (PLL) circuit is indispensable in producing high-speed on-chip clock signals in an IC. For safety-critical applications, fault and soft-error tolerance is often a desirable feature. However, how to achieve that goal for a PLL circuit remains a challenge. In this paper, we address this challenge with a TMR-based FET PLL design. In this thesis, we first show that a naïve FET-PLL using the Triple-Module Redundancy (TMR) technique cannot work unless the input of the voter is synchronized, by using a Synchronization-before-Voting TMR Scheme, the careless FET-PLL can tolerant fault and soft error. Furthermore, we enhance it with careful Phase Detector placement and using a Sense Amplifier to optimize the performance and area overhead. Through careful placement, the peak-to-peak jitter over 1000 clock cycles in PLL can be reduced from 25ps using the careless FET-PLL to 12ps, and by using Sense Amplifier the Area Overhead compared to primitive PLL can be reduced from 687% to 675%
Our unique contribution is a “synchronization-before-voting” scheme so that the fault and soft-error tolerance and the jitter performance can be maintained at the same time. Post-layout simulation using a 90nm CMOS process demonstrates that our PLL can indeed withstand the attack of online faults as well as soft errors without suffering from significant jitter performance loss.

Abstract ii
摘要 iii
誌謝辭 iv
Content v
List of Figures vii
List of Tables ix
Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Thesis Organization 4
Chapter 2 Preliminaries 5
Chapter 3 Proposed Fault and Soft-Error Tolerance Scheme for PLL 9
3.1 Predicament of Naïve TMR-based PLL 9
3.2 FET-PLL using a Synchronization-before-Voting TMR Scheme 11
3.2.1 Architecture of FET-PLL 11
3.2.2 Operation of FET-PLL 13
3.2.3 Detail component of FET-PLL 15
Chapter 4 Experimental Results of FET-DLL 29
4.1 Layout and simulation result under normal conditions 29
4.2 Jitter performance under different process corner 32
4.3 Jitter performance of Monte Carlo simulation 33
4.4 Impact of various Phase detectors 34
4.5 Simulation of Fault scenarios 37
4.5.1 Scenario 1 38
4.5.2 Scenario 2 39
4.5.3 Scenario 3 41
4.5.4 Scenario 4 42
Chapter 5 Conclusion 45
References 46

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