無線通訊技術的快速發展大幅改善人類的生活模式，舉例來說，名聞遐邇的5G通訊技術提供更快的資料傳輸速度及更低的延遲，應用層面廣泛。以通訊信號傳輸來說，必不可少的正是類比數位轉換器，伴隨著半導體製程的演進，為了達成中高解析度及中速的目標，熱門的選擇無疑是連續漸進式類比數位轉換器。

一個採用次階式概念的高速混合型連續漸進式類比數位轉換器實現於此論文中，用近似次階式的電路架構為基礎，運用多個比較器，再加上錯誤容忍的技巧，使得速度可以有效的提升。其中，錯誤容忍的演算法是採用二進位重組的方式，它不只可以用來容忍電容陣列切換後，尚未穩定就進行下一次比較而產生的錯誤，還可以容忍不同比較器之間不匹配的錯誤。另外，此電路也採納回切已切換電容的方法，以補償電容不匹配問題。

本論文的成果是採用台積電65奈米CMOS標準製程，此連續漸進式類比數位轉換器在1.2伏特下操作，輸入訊號的峰對峰值為2.16伏特，是一個十位元每秒取樣兩億五千萬次的設計。當輸入訊號頻率接近奈奎斯特頻率時，模擬結果是: 平均功率消耗是2.867 mW，有效位元數是9.75位元。

The rapid development of wireless communication technology has greatly improved people's lifestyles. For example, the widely acclaimed 5G communication technology provides faster data transmission speed and lower latency in broad applications. Among them, the analog-to-digital converter (ADC) is an essential circuit in communication systems. With the evolution of semiconductor processes, the successive approximation register (SAR) ADC has been a prevalent option for medium-speed and medium-to-high-resolution applications.

The presented high-speed SAR ADC utilizes multiple comparators in a structure similar to a sub-ranging architecture and error-tolerant technique to effectively improve the speed. Among them, the error-tolerant technique uses the binary-scaled recombination search algorithm, which can not only tolerate the incomplete settling errors but also the offset errors between different comparators. Additionally, this circuit also employs the correlated reversed switching (CRS) technique to compensate for capacitor mismatch.

This work, a 10-bit 250-MS/s hybrid SAR ADC, is implemented in a TSMC 65-nm CMOS technology, with an operating voltage of 1.2 V and an input signal with peak-to-peak voltage (Vp-p) of 2.16 V. Near the Nyquist frequency, the simulation results present that the simulated ENOB is 9.75 bits with the average power consumption of 2.867 mW.

摘要 i
Abstract ii
致謝 iii
Contents iv
List of Figures x
List of Tables xv
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization of the Thesis 2
Chapter 2 Fundamentals of ADCs 3
2.1 Introduction of ADCs 3
2.1.1 Nyquist Sampling and Oversampling 3
2.1.2 Quantization Error 6
2.1.3 Resolution 8
2.2 Performance Indexes of ADCs 8
2.2.1 Static Specifications 9
2.2.1.a Offset Error 9
2.2.1.b Gain Error 10
2.2.1.c Differential Nonlinearity (DNL) 11
2.2.1.d Integral Nonlinearity (INL) 12
2.2.2 Dynamic Specifications 13
2.2.2.a Signal-to-Noise Ratio (SNR) 13
2.2.2.b Signal-to-Noise and Distortion Ratio (SNDR) 14
2.2.2.c Effective Number of Bits (ENOB) 14
2.2.2.d Spurious-Free Dynamic Range (SFDR) 15
2.2.2.e Total Harmonic Distortion (THD) 15
2.2.2.f Effective Resolution Bandwidth (ERBW) 16
2.2.2.g Figure of Merit (FoM) 16
2.3 Nyquist-Rate ADCs 17
2.3.1 Flash ADC 17
2.3.2 Sub-ranging ADC 19
Chapter 3 SAR ADCs 20
3.1 Operation of SAR ADCs 20
3.2 Fundamental Techniques and principles of SAR ADCs 21
3.2.1 Synchronous and Asynchronous 21
3.2.2 Bottom-Plate Sampling and Top-Plate Sampling 25
3.2.3 Charge-Redistribution 26
3.3 Capacitive-DAC (C-DAC) Switching Algorithm 28
3.3.1 Conventional Switching Algorithm 29
3.3.2 Split-Capacitor Switching Algorithm 31
3.3.3 Monotonic Switching Algorithm 33
3.3.4 Switchback Switching Algorithm 35
3.3.5 Comparison of Switching Energy 37
Chapter 4 High-Speed SAR ADCs 38
4.1 Timing Limit 38
4.1.1 The Comparison Time of Comparator 39
4.1.2 The Reset Time of Comparator 41
4.1.3 The Settling Time of DACs 42
4.1.4 The Logic Delay Time of Digital Circuits 43
4.2 Sub-ranging Architecture 45
4.3 Multi-Comparator Architecture 47
4.4 Error-Tolerant Design 49
4.4.1 Redundancy Search Algorithm 49
4.4.1.a Non-Binary Search Algorithm 50
4.4.1.b Binary-Scaled Compensation Search Algorithm 52
4.4.1.c Binary-Scaled Recombination Search Algorithm 55
Chapter 5 A 10-Bit 250-MS/s Hybrid SAR ADC 58
5.1 Architecture 58
5.2 Bootstrapped Switch (S/H) 60
5.2.1 Design Considerations 60
5.2.2 Operation 62
5.3 Dynamic Comparator 64
5.3.1 Design Considerations 64
5.3.1.a Offset 64
5.3.1.b Speed & Accuracy 65
5.3.1.c Kickback Noise 67
5.3.2 Coarse Comparator 67
5.3.2.a Operation 68
5.3.2.b Simulation Results 70
5.3.3 Fine Comparator 70
5.3.3.a Operation 72
5.3.3.b Simulation Results 73
5.4 Capacitive-DAC (C-DAC) 75
5.4.1 Switchback Switching Method 75
5.4.2 Redundancy Technique 75
5.4.3 Correlated Reversed Switching (CRS) Technique 77
5.4.3.a Behavior Model Simulation Results 80
5.4.4 Layout 80
5.5 Digital Circuits 82
5.5.1 Asynchronous Digital Control Logic Circuits 85
5.5.2 Differential Digital Latches 86
5.5.3 CRS Logic in the C-DAC Buffer 88
5.5.4 Additional Digital Error Correction (ADEC) Decoder 88
5.6 Simulation Results 90
5.6.1 Layout 90
5.6.2 Post-Layout Simulation 92
Chapter 6 Conclusions and Future Works 95
Reference 96

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