近來年，為了減少成本與更高密度的資料儲存，三維NAND型快閃記憶體(3D NAND flash) 已成為市場主流的發展方向之一。3D NAND與傳統的2D NAND不同，3D NAND將儲存單元垂直堆疊在一起，形成三維的結構。這種結構使得同樣大小的晶片可以儲存更高密度的資料。然而當記憶體架構從二維轉到三維時，儲存單元之間的讀寫干擾將變得更嚴重，也導致新型態的干擾風險產生，因此需要一種有效的內建自我測試(BIST)來保證其品質與可靠性。
在這篇論文裡，我們提出針對3D NAND 的內建自我測試(BIST)架構。首先，我們根據現有的3D NAND錯誤模型，考慮了位址不規則性的影響，對其進一步的修改，使其能更符合實際上3D NAND型快閃記憶體產品的運作。接著，我們利用現有的三維快閃記憶體錯誤模擬器RAMSES-3DFT進行模擬，以驗證Diagonal-3DFT演算法對於修正後的3D NAND錯誤模型的有效性。基於這些研究結果，我們提出了能夠支援Diagonal-3DFT測試演算法的BIST架構，該演算法可以在實現高覆蓋率的同時，保持較高的測試效率，因此在減少測試成本的情況下可以提高3D NAND型快閃記憶體的可靠性和測試效率。

In recent years, the three-dimensional (3D) NAND flash has become one of the mainstream development directions in the semiconductor memory market, which reduces costs and achieves higher storage density. Unlike the traditional 2D NAND flash, a 3D NAND flash stacks storage cells in the vertical dimension to form a 3D structure. This structure allows flash memory chips of the same size to achieve higher storage density. However, when we turn the 2D memory architecture into 3D, the read/write disturbance between storage cells becomes more severe, leading to new types of potential disturbance faults. Therefore, an effective built-in self-test (BIST) is needed to ensure its reliability.
In this thesis, we propose a BIST architecture, which is specifically for the 3D NAND flash memory. First, we modify the existing 3D NAND fault models by considering the impact of address scrambling, aiming to better match the actual operation of 3D NAND flash products. Next, we use existing three-dimensional flash memory fault simulator, RAMSES-3DFT, to verify the effectiveness of the Diagonal-3DFT algorithm on the modified 3D NAND fault models. Based on these research findings, we present a BIST architecture that supports a test algorithm based on the concept of Diagonal Test, called the Diagonal-3DFT, which can achieve high fault coverage while maintaining short testing time. The BIST scheme improves the quality and reliability of 3D NAND flash products, while reducing their testing costs.

中文摘要 1
Abstract ii
Contents iii
Chapter 1 Introduction 1
1.1 Motivation and Objective 1
1.2 Thesis Organization 2
Chapter 2 Background 3
2.1 3D NAND Flash Cell 3
2.2 3D NAND Flash Architectures 4
2.2.1 BiCS (Bit Cost Scalable) 6
2.3 3D NAND Fault Models 8
2.4 Diagonal 3D NAND Flash Test Algorithm (Diagonal-3DFT) 17
Chapter 3 A Built-In Self-Test design for 3D NAND Flash Memory 22
3.1 Previous Work (BIST for Flash Memory) 22
3.2 The 3D NAND Flash Memory Module with BIST 24
3.3 The Built-In Self-Design 25
3.4 Simulation Results 27
Chapter 4 Experiment Results 29
4.1 BIST Area Complexity 29
4.2 Test Complexity 30
4.4 RAMSES-3DFT simulation results 31
4.4 Discussion 32
Chapter 5 Conclusions and Future Work 34
5.1 Conclusions 34
5.2 Future Work 34
Bibliography 36

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