本論文提出應用於有線通訊之操作在 6.4GHz 具有二位元相位檢測器的全數位鎖相迴
路又稱為 bang bang PLL，與數位式鎖相迴路有所不同，一般的數位式鎖相迴路的電路架構組成:相位檢測器(Phase detector, PD)、充電泵(Charge pump)、迴路濾波器(Loop filter)、壓控振盪器(Voltage control oscillator, VCO)與頻率除頻器(frequency divider)，而本論文的電路架構組成:二位元相位檢測器(Binary phase detector, BPD)、數位迴路濾波器(Digital loop filter)、數位控制振盪器(Digital control oscillator, DCO)、頻率除頻器(frequency divider)。Bang-bang 鎖相迴路相較於傳統式與數位式鎖相迴路的優點，有更好的雜訊容忍度，且在
製程轉移上也相對容易。

Bang bang 架構全數位鎖相迴路的系統分析相對於其他架構上困難很多，因此本論文
透過行為模組模擬，進行系統模擬並比較多組數據的結果，可透過模擬結果及實際應用之需求，找出最適當的參數。本論文使用 TSMC 65 nm CMOS 製程，且供應電源電壓為 1.2 V 的環境下，實現一個應用於有線通訊之操作在 6.4GHz 具有數位控制振盪器的全數位鎖相迴路。輸入資料為100MHz 石英振盪器，頻率合成時脈速率為 6.4GHz

This paper proposes a all digital phase-locked loop with a two-bit phase detector at 6.4GHz for wired communication, also known as bang-bang PLL, which is different from the traditional digital phase-locked loop. The circuit structure of the loop consists of a phase detector (PD), a charge pump (CP), a loop filter (LF), a voltage control oscillator (VCO) and a frequency divider (DIV), and the circuit structure of this paper consists of: binary phase detector (BPD), digital loop filter (DLF), digital control oscillator (DCO), frequency divider (DIV).
Compared with traditional analog and traditional digital PLLs, Bang-bang PLLs have better noise tolerance and are relatively easy to process transfer.
The system analysis of bang-bang PLL is much more difficult than other architectures. Therefore, in this paper, the behavior module simulation is used to simulate the system and compare the results of multiple sets of data. The most appropriate parameters can be found
through the simulation results and practical application requirements. .This paper uses TSMC 65 nm CMOS process, and the supply voltage is 1.2 V to realize a all digital phase-locked loop with a digitally controlled oscillator operating at 6.4 GHz for wired communication. The input data is a 100MHz quartz oscillator, and the frequency synthesis clock rate is 6.4GHz.

摘要 I
Abstract II
目錄 III
圖目錄 V
表目錄 VIII
第一章 緒論 1
1.1研究動機 1
1.2論文大綱 2
第二章 鎖相迴路架構介紹 3
2.1簡介 3
2.2類比式鎖相迴路 4
2.3數位式鎖相迴路 5
2.4全數位鎖相迴路 19
2.5鎖相迴路之比較 23
第三章 電路設計與實現 25
3.1簡介 25
3.2二位元相位檢測器 26
3.3數位濾波器 32
3.4數位控制振盪器 34
3.5整數除頻器 39
第四章 模擬結果與系統模擬 40
4.1簡介 40
4.2二位元相位檢測器模擬結果 41
4.3數位濾波器模擬結果 44
4.4數位控制振盪器模擬結果 47
4.5整數除頻器模擬結果 52
4.6系統模擬結果 53
4.6.1 電路模擬 53
4.6.2 行為模組模擬 57
第五章 結論 59
5.1總結 59
5.2未來展望 60
5.3參考文獻 60

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