近年來，隨著莫爾定律，非揮發性快閃記憶體尺寸逐年微縮，並廣泛應用於許多產品，同時，為了不斷提升快閃記憶體特性，有許多方法被提出，例如無接面式通道、矽化鍺與鍺通道、能帶工程(bandgap engineering)等。本論文使用Synopsys Sentaurus TCAD軟體對三閘極電荷捕捉式快閃記憶體元件進行模擬研究，包含使用矽化鍺與鍺通道，穿隧層之能帶工程應用，高介電質材料堆疊於電荷陷阱層之特性探討。
鍺作為通道材料因具備較小的能隙(~0.66 eV)，可以提供更多的載子在快閃記憶體寫入/抹除操作期間，進一步提升電荷陷阱式快閃記憶體的操作速度，因此在第一部分研究中，為模擬能帶工程應用於穿隧層之電荷陷阱式快閃記憶體元件特性，並搭以三閘極無接面式鍺通道之結構，包含使用氧化鍺、氧化鋁、二氧化矽材料作為穿隧層材料，同時探討元件內部物理機制。模擬結果顯示，具有氧化鍺、氧化鋁、二氧化矽堆疊穿隧層元件擁有較快操作速度與較佳電荷保持力特性，分析因其擁有較大的注入電流、較低的穿隧能障、較大的穿隧電場，以及擁有較大的物理厚度與較高的穿隧層能障於電荷保持力測試中。
由於過去文獻尚未討論鍺含量同時對於掩埋式通道與其通道界面氧化層的影響，因此了解鍺同時在掩埋式通道與其通道界面氧化層內的物理機制，對於多晶矽電荷捕捉式快閃記憶體元件的操作特性至關重要，在第二部分研究中，為模擬使用矽化鍺與鍺作為通道材料同時搭以其界面氧化層的元件特性，並探討元件內部物理機制。模擬結果顯示，鍺通道元件擁有較快之操作速度，可歸因於通道與穿隧層界面之二氧化鍺能障較低，且橫跨在通道上的電場較大，將載子大量集中於通道與穿隧層界面處，可靠度方面，因穿隧氧化層之二氧化鍺能障較低，使得元件的電荷保持力特性較差。
對於高性能的多晶矽電荷捕捉式快閃記憶體而言，抹除速度一直是個瓶頸，為了提升電荷捕捉式快閃記憶體元件的抹除速度，文獻提出了許多種方法，像是使用高介電(high-k)材料取代傳統Si3N4作為元件電荷陷阱層，因此在第三部分研究中，為模擬高介電質材料堆疊於電荷陷阱層的元件特性，包含使用二氧化鋯、氮氧化鋯、鋁摻雜氮氧化鋯，堆疊氮化矽作為電荷陷阱層，並探討元件內部物理機制。模擬結果顯示，二氧化鋯元件表現出最快的寫入/抹除速度，歸因於二氧化鋯缺陷能階較淺，但也因此表現出待改善的電荷保持力特性。而藉由使用氮氧化鋯可改善電荷保持力特性，但氮氧化鋯缺陷能階較深，使元件表現出最慢的抹除速度，最後，鋁摻雜氮氧化鋯元件則表現出可接受的抹除速度，以及不錯的電荷保持力特性。

In recent years, the dimension of non-volatile flash memory device is continuously scaling with Moore's law and the devices are widely applied on many products. To continuously enhance operation characteristics of flash memory devices, several efficient methods have been proposed, such as junctionless (JL) channel, SiGe channel, Ge channel, and bandgap engineering. In this dissertation, the tri-gate charge-trapped (CT) flash memory devices were simulated and studied by Synopsys Sentaurus TCAD. The main themes include SiGe and Ge as channels, bandgap-engineering applied in tunneling layers and high-k dielectrics as stacked trapping layers.
Since germanium (Ge) as channel material has a smaller bandgap (~0.66 eV), more carriers are provided during program/erase operations, which can improve the operation speed of CT flash devices. Therefore, in the first part, bandgap-engineering in tunneling layers on operation characteristics of flash memory devices with JL Ge channel and tri-gate structure were studied by using simulation tool, from which the physical mechanisms were also discussed. The devices with GeOx, Al2O3, SiO2 as stacked tunneling layers were investigated. The results show that the device with GeOx/Al2O3/SiO2 (GAS) stacked tunneling layers have faster operation speeds and better retention performance than other samples, because the GAS device has a higher injection current, and a larger electric field across the tunneling layers. Also, the GAS device has a larger physical thickness and a higher tunneling barrier during the retention test.
The effects of Ge content in both buried channel and tunneling oxide on CT flash memory device were rarely seen. Since Ge atoms would generally exist in both buried channel and tunneling oxide of CT flash memory device with Ge-based channel, it is important to understand their effects on operation characteristics of devices. In the second part, effects of Si1-xGex and Ge as the channel material on operation characteristics of CT-flash device and physical mechanisms were studied with simulation. The results indicate that the device with Ge channel has faster operation speeds, due to the lower energy barrier of GeO2 and larger electric field across the buried channel, which accumulate many carriers at the interface of the buried channel and tunneling layer. Due to the lower energy barrier of GeO2, the device with Ge channel has worse retention characteristics during the reliability test.
The erasing speed is the bottleneck for high-performance poly-Si CT flash devices. Several approaches were proposed to increase the erasing speed of CT flash devices, such as using high-k material to replace traditional Si3N4 as a trapping layer. Therefore, in the third part, the high-k dielectrics as a stacked trapping layer on operation characteristics of CT-flash devices and physical mechanisms were studied with simulation. The high-k dielectrics including ZrO2, ZrON, ZrAlON are stacked with Si3N4 as trapping layers in this study. The results indicate that the device with Si3N4/ZrO2 stacked trapping layer has the fastest program/erase speeds, but its retention performance needs improvement, because the trap energy level of ZrO2 is shallow. Besides, retention characteristics of device can be improved by adopting Si3N4/ZrON trapping layer, which however may cause slow erasing speeds, due to the deep trap energy level of ZrON. Finally, the device with Si3N4/ZrAlON stacked trapping layer has acceptable erase speeds and good retention characteristics as well.

摘要 i
Abstract iii
誌謝 v
目錄 vi
圖目錄 ix
表目錄 xiii
第 1 章 序論 1
1.1. 非揮發性記憶體 1
1.2. 多晶矽通道與三維(3D)記憶體 2
1.3. 高介電材料與能帶工程 3
1.3.1 電荷陷阱式快閃記憶體 3
1.3.2 高介電材料 3
1.3.3 能帶工程 4
1.4. 無接面快閃記憶體元件 5
1.5. 矽化鍺與鍺掩埋式通道於快閃記憶體的應用 6
1.6. 鍺薄膜特性 7
1.7. 各章摘要 8
第 2 章 電荷陷阱式快閃記憶體基本特性與模擬軟體 19
2.1. 載子穿隧機制 19
2.1.1 Fowler-Nordheim (FN)穿隧 19
2.1.2 直接穿隧 (Direct tunneling, DT) 20
2.1.3 修正FN穿隧(MFN) 21
2.2. Sentaurus TCAD模擬軟體介紹 21
2.2.1 軟體基本介紹 21
2.2.2 模擬物理模型 23
2.3. 快閃記憶體基本操作原理 24
2.4. 快閃記憶體可靠度特性 25
2.4.1元件耐久力 25
2.4.2 電荷保持力 26
第 3 章 堆疊穿隧層應用於無接面鍺通道電荷陷阱式快閃記憶體之模擬研究 31
3.1. 研究背景與實驗結果介紹 32
3.1.1 研究背景介紹 32
3.1.2 實驗元件特性介紹 33
3.2. 模擬元件參數與物理模型 33
3.3. 模擬結果與討論 34
3.3.1 模擬堆疊穿隧層應用於無接面鍺通道快閃記憶體操作速度特性 34
3.3.2 模擬堆疊穿隧層應用於無接面鍺通道快閃記憶體電荷保持力特性 35
3.4. 本章結論 36
第 4 章 矽化鍺與鍺掩埋式通道電荷陷阱式快閃記憶體元件之模擬研究 46
4.1. 研究背景與實驗結果介紹 47
4.1.1 研究背景介紹 47
4.1.2 實驗元件特性介紹 47
4.2. 模擬元件參數與物理模型 49
4.3. 模擬結果與討論 50
4.3.1 模擬有/無掩埋式通道元件操作速度特性 50
4.3.2 模擬有/無掩埋式通道元件電荷保持力特性 53
4.4. 本章結論 54
第 5 章 將氮與鋁摻入氮化矽/二氧化鋯堆疊電荷陷阱層對無接面多晶矽通道電荷陷阱式快閃記憶體之模擬研究 66
5.1. 研究背景與實驗結果介紹 67
5.1.1 研究背景介紹 67
5.1.2 實驗元件特性介紹 68
5.2. 模擬元件參數與物理模型 69
5.3. 模擬結果與討論 70
5.3.1 模擬堆疊電荷陷阱層無接面多晶矽通道快閃記憶體操作速度特性 70
5.3.2模擬堆疊電荷陷阱層無接面多晶矽通道快閃記憶體電荷保持力特性 72
5.4. 本章結論 72
第 6 章 結論 82
參考文獻 84

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