科技的快速發展與半導體產業密不可分，像是在網絡物理系統平台中，物聯網扮演著不可或缺的角色，為了收集大數據，並且在雲計算中進行存儲和分析，物聯網設備的數量將增長到數萬億甚至更多，因此高性能和低功耗的半導體元件是被需要的，隨著半導體技術節點的微縮，我們期望在集成電路上放置更密集的半導體元件，但隨之而來的卻是製程技術面臨困難以及元件微縮下的物理限制，而如何去解決這些問題至今仍是個備受矚目的議題，因此有不少學術研究團隊正朝向這方面進行研究，並在半導體材料與結構相關領域發表了豐碩的成果，期望能為當今科技的進步做出貢獻。
本篇論文運用了絕緣層覆矽基板以及鍺磊晶技術，在基板上製作出鍺堆疊奈米線，利用鍺的原子排列特性，透過簡化製程將通道蝕刻成菱形奈米線結構，並加入鐵電效應以及環繞式閘極的設計，來提升載子遷移率、提高驅動電流、改善次臨界斜率與增加閘極控制能力，使這些技術能結合到未來的高功率、低功耗元件上。
本篇論文提出一種自發性的摻雜方式來形成Ge:HfO2鐵電層，只需透過Ge材料本身的熱反應，便能使微量的Ge摻雜進HfO2內，能夠降低製程上的時間與成本，並透過電容的材料分析與電性量測來證實鐵電電容的形成，其中針對了界面層形成方式、退火溫度以及氧化層厚度的變化進行討論，接著，我們將鐵電電容結構應用於電晶體上，為了探討自發性摻雜對於High-k/ Ge界面處缺陷的影響，這部分共設計了兩種退火溫度，透過電晶體性能的重要指標來進行分析，最終成功的製作出了N型與P型環繞式閘極鍺堆疊奈米線鐵電電晶體，經由鐵電效應改善了電晶體的次臨界斜率，達到了提升電晶體性能的效果。

The rapid development of technology is inseparable from the semiconductor industry. For example, in the Cyber-Physical System(CPS) platform, the Internet of Things(IoT) plays an indispensable role. In order to collect, store and analyze big data in cloud computing, the number of IoT devices will increase to trillions or more, so high-performance and low-power semiconductor devices are required. With the continuous development of semiconductor technology nodes, we hope to place denser semiconductor devices on integrated circuits. However, with the scaling of devices, process technology faces difficulties and physical limitations. How to solve these problems has always been people's concern. Therefore, many academic research teams are paying attention to this field and have published various results of designing semiconductor materials and device structures, hoping to contribute to the advancement of science and technology.
In this paper, the Silicon on Insulator(SOI) and germanium epitaxy technologies are used to prepare germanium stacked-nanowire on the substrate. Utilizing the atomic arrangement of germanium, we can fabricate the diamond-shaped nanowire structure through a simple process. The addition of ferroelectric materials and Gate-All-Around structure to improve the carrier mobility, drive current, subthreshold swing and gate controllability, so that these technologies can be combined with future high-power and low-power consumption devices.
This paper proposes the self-induced doping method to form the Ge:HfO2 ferroelectric layer. Through the thermal reaction of the Ge material itself, a small amount of Ge can be doped into HfO2, which can reduce the time and cost of the process. Confirm the formation of ferroelectric capacitors through the material analysis and electrical measurement. The changes in interlayer formation, annealing temperature and oxide thickness are also discussed. Finally, the ferroelectric capacitor structure was successfully applied to transistors. To explore the effect of self-induced doping on high-k/ Ge interface defects, two annealing temperatures are designed in this paper. After analysis, N-type and P-type Gate-all-around Ge Stacked-Nanowire Ferroelectric FET were successfully fabricated, and the performance of the devices were improved, especially the steep subthreshold swing was observed through the ferroelectric effect.

中文摘要------------------------------------------i
Abstract-----------------------------------------iii
致謝----------------------------------------------v
目錄----------------------------------------------vi
表目錄--------------------------------------------viii
圖片目錄------------------------------------------ix
第一章--------------------------------------------1
簡介----------------------------------------------1
1-1 摩爾定律的挑戰(Moore’s Law)--------------------1
1-2 高遷移率之通道材料-----------------------------4
1-3 鍺磊晶於SOI晶圓上------------------------------5
1-4 High K材料在鍺場效電晶體之應用------------------7
1-5 奈米線電晶體(NWFET)---------------------------10
1-6 緊密堆疊之奈米線結構---------------------------12
1-7 表面臭氧處理----------------------------------14
1-8 鐵電材料之電晶體應用---------------------------16
1-9 研究動機--------------------------------------20
1-10 論文組織-------------------------------------25
第二章--------------------------------------------27
鐵電電晶體(FE-FET)之機制介紹-----------------------27
2-1 MOSFET之操作原理與重要參數---------------------27
2-2 次臨界斜率(SS)的突破--------------------------30
2-3 鐵電負電容效應--------------------------------32
2-4 鐵電正電容效應--------------------------------34
2-5 自發性摻雜 (Self-induced doping)--------------37
第三章-------------------------------------------40
MIS電容之製程結構與特性分析------------------------40
3-1 不同IL形成方式之電容比較-----------------------40
3-1.1 結構與製成流程------------------------------40
3-1.2 材料分析------------------------------------43
3-1.3 不同IL形成方式之電容特性---------------------45
3-2 不同氧化層厚度之電容比較-----------------------50
3-2.1 結構與製成流程------------------------------50
3-2.2 不同氧化層厚度之電容特性---------------------52
3-2.3 退火溫度對Dit值之影響-----------------------55
第四章-------------------------------------------57
環繞式閘極鍺堆疊奈米線鐵電電晶體(Ge-GAAFET)---------57
4-1 退火溫度對於電晶體特性之影響-------------------57
4-1.1 結構與製程流程------------------------------57
4-1.2 SEM、TEM與EDS之材料分析---------------------61
4-2 N型與P型電晶體特性之比較-----------------------67
4-2.1 結構與製程流程------------------------------67
4-2.2 電特性分析----------------------------------70
第五章-------------------------------------------78
結論---------------------------------------------78
參考文獻------------------------------------------80

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