在第五代行動通訊中，毫米波多輸入多輸出系統被應用來滿足高資料產出量的需求，然而當有大量天線的時候，全數位預編碼的RF鏈在輸入多輸出系統中造成大量的成本，所以混合式預編碼的架構就被用在巨量天線的多輸入多輸出系統來減少RF鏈的數量。傳送在毫米波的訊號有大量的路徑耗損，所以三維多輸入多輸出系統被應用來組成有水平及垂直方向自由度的波束以及中更多能量，張量將可能是一個好的代數工具來表示三維的通道。此篇論文提出一種基於張量的混合式預編碼追蹤演算法來增加頻譜效率，張量分解及正交的特性可以使通道對角化，為了在連續時間的通道中追蹤預編碼，所以將原本的高維度奇異值分解(Higher-order singular value decomposition)由高維正交遞迴(Higher-order orthogonal iteration)取代。此篇論文用QuaDRiGa 通道模型來模擬所提出的演算法，模擬結果顯示所提出的演算法的頻譜效率在SNR低的區域有比較好的表現以及所提出的演算法適合在稀疏性較高的通道被使用。我們也提出了一個硬體架構支援64根傳送天線被實現在FPGA-xcvu19p-fsvb3824-1-e，這個混合式預編碼的處理器的時脈頻率為83.33 MHz，資料產出量可達到每秒 33.280/16.640/11.093 k 個預編碼當演算法遞迴1/2/3次得時候，此資料產出量可以達到通道同調時間的需求。

The millimeter-wave (mmWave) multiple-input multiple-output (MIMO) systems are applied to satisfy the high-throughput requirement in the fifth-generation communication. However, the RF chains of fully digital precoding cost a lot in MIMO systems when the number of antennas becomes massive. The architectures of hybrid precoding are used in massive MIMO systems to reduce the RF chain number. The signals in mmWave have significant path loss, so a three-dimensional (3D) MIMO is applied to form beams in two dimensions to gain more power. Tensor may be a suitable algebraic object to represent a 3D-MIMO channel.
This thesis proposed a tensor-based hybrid precoding tracking algorithm for 3D-MIMO systems to improve spectral efficiency. The tensor decomposition and all-orthogonal property can diagonalize the 3D-MIMO channel. To track the precoder in continuous-time channels, we replace higher-order singular value decomposition (HOSVD) with higher-order orthogonal iteration (HOOI). This thesis simulates the proposed hybrid precoding with the QuaDRiGa channel model in different scenarios. Simulation results show that the spectral efficiency of the tensor-based hybrid precoding tracking is improved in the low SNR regions, and the tensor-based hybrid precoder is suitable for sparse channels.
In addition, we propose the architecture of the proposed hybrid precoding tracking. This architecture supports 64 antennas and is implemented on FPGA-xcvu19p-fsvb3824-1-e. The hybrid precoding processor can operate with 83.33MHz clock speed. The throughput can achieve 33.280/16.640/11.093 k precoders per second for the number of iteration is 1/2/3, respectively, to satisfy the coherence time requirement.

Abstract
Contents
1 Introduction ...................................................... 1
1.1 Millimeter Wave 3D-MIMO Systems ................................ 1
1.2 Research Motivation ............................................ 2
1.3 Organization of This Thesis .................................... 3
1.4 Notations ...................................................... 4
2 Tensor Definition and Higher-Order Singular Value Decomposition .. 5
2.1 Basic Definition of Tensor ..................................... 5
2.1.1 Tensor ....................................................... 5
2.1.2 Rank of an N-Order Tensor .................................... 6
2.1.3 Scalar product, orthogonality, and norm of tensors ........... 7
2.1.4 N-mode product ............................................... 8
2.2 Higher-Order Singular Value Decomposition ...................... 9
2.2.1 Matrix SVD ................................................... 9
2.2.2 Higher-order SVD ............................................. 10
2.2.3 Low-Rank Approximation Property .............................. 11
3 Channel Model and Hybrid Precoding Algorithm for MIMO Systems .... 15
3.1 QuaDRiGa Channel Model ......................................... 15
3.2 SVD-Based Digital Precoding .................................... 20
3.3 Hybrid Precoding ............................................... 22
3.4 Hybrid Precoding based on Tensor Decomposition ................. 25
4 Proposed Hybrid Precoding Tracking Algorithm ..................... 29
4.1 Proposed tensor-based Hybrid Precoding ......................... 29
4.2 Hybrid Precoding Tracking Algorithm ............................ 32
4.2.1 Higher-Order Orthogonal Iteration ............................ 32
4.2.2 Proposed tensor-based Hybrid Precoding Tracking .............. 35
4.3 Simulation Result and Analysis ................................. 36
5 VLSI Architecture ................................................ 45
5.1 System Architecture ............................................ 45
5.2 HOOI Processor ................................................. 49
5.3 Hybrid Precoder Processor ...................................... 53
5.4 Timing Schedule ................................................ 55
5.5 Synthesis Result ............................................... 56
6 Conclusion ....................................................... 59
References ......................................................... 61

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