LDMOS做為Power ICs中最常使用的功率元件，其效能會影響電路的效率，一般對於LDMOS效能的評量常以特徵導通電阻(Specific on-resistance, R_(on,sp ))與崩潰電壓為主，較少討論元件的動態特性與可靠度。本論文主要利用TCAD模擬來分析元件分別在上橋與下橋操作情形下電壓、電場以及電流的分布情形，並比較其中的異同。之後再針對元件結構設計進行調整並搭配TCAD模擬以及實際量測確認結構的改變對元件特性的影響，最後再透過熱載子應力測試來確認元件的可靠度。
實際量測結果顯示，Split gate結構可以大幅降低元件開啟時所需的電荷量，降幅約為40%，對於切換速度的提升有所幫助。崩潰電壓的部分隨著元件閘極與汲極間距離加長，耐壓可以有所提升，若在汲極端加上NWIO結構可以使閘極電壓3.3伏特時的崩潰電壓上升14.1%。在可靠度的部分，量測結果顯示Split gate結構與汲極端加NWIO結構的考靠度表現皆不會比標準結構差。綜合來說以Split gate搭配汲極端加上NWIO結構並選擇適當的閘極與汲極間距離可以有最均衡的元件特性。

The performance of a LDMOS is critical to the efficiency of Power ICs, since it is the most widely used power device in these applications. LDMOS is typically evaluated by R_(on,sp) and breakdown voltage and its dynamic characteristics and reliability are also intensively studied. The main objective of this thesis is using TCAD simulation to analyze the voltage, electric field and current distribution device LDMOS in the high-side and low-side operation conditions, and compare the similarities and differences. Then, some different structures are simulated and measured to confirm the predicted influences of the structure change on the electrical characteristics. Finally, the reliability of the devices are investigated through the hot carrier stress.
The measurement results show that split gate can reduce 40% the amount of gate charge required during the device turn on, which is helpful for the improvement of the switching speed. As the distance between gate and drain of the device increases, the breakdown voltage can increase. If NWIO implant is added at drain side, the breakdown voltage at a gate voltage of 3.3 volts can be increased 14%. As for the reliability, measurement results show that the reliability performance of split gate and NWIO drain side structure is comparable to the standard structure. In short, combining split gate and NWIO drain side with an appropriate gate drain distance can have the most balanced device characteristics.

中文摘要
Abstract
目錄
圖目錄
表目錄
第一章 序論 1
1.1 研究動機 1
1.2 論文大綱 2
1.3文獻回顧 3
1.3.1 元件基本原理 3
1.3.2 RESURF(Reduced surface field)技術 5
1.3.3 場板(Field plate)效應 5
1.3.4 閘極電荷(Gate charge) 7
1.3.5 熱載子效應 8
第二章 元件結構與模擬 10
2.1 基本介紹 10
2.2 物理模型 11
2.3 元件結構模擬 16
2.4 元件特性模擬 18
2.4.1 Id -Vg模擬 18
2.4.2 Id -Vd模擬 21
2.4.3 崩潰電壓模擬 21
2.4.4 電容模擬 23
2.4.5 Gate charge模擬 24
第三章 動態特性模擬與分析 28
3.1 Mixed-mode介紹 28
3.2 動態特性模擬 29
3.3 上橋元件特性分析 31
3.4 元件在上下橋操作時之特性比較 37
第四章 元件結構設計模擬與量測 45
4.1 基本介紹 45
4.2 元件結構設計模擬 48
4.3 量測結果 55
4.3.1 量測儀器設定 55
4.3.2 基本電性量測結果分析 56
4.3.3 Gate charge量測結果分析 56
4.3.4 Crss 量測結果分析 57
4.3.5 元件之SOA邊界 57
4.3.6 元件之BFOM與動態特性FOM 65
第五章 元件熱載子衰退現象 67
5.1 基本介紹 67
5.2 Kirk effect 69
5.3 可靠度特性 71
5.4 模擬分析 76
第六章 結論與未來展望 85
6.1 結論 85
6.2 未來展望 86
參考文獻 87

[1]B.J. Baliga, “An overview of smart power technology,” IEEE Trans. Electron Devices, vol. 38, no.7, pp. 1568-1575, 1991.
[2]C. Contiero, P. Galbiati, M. Palmieri, L. Vecchi, “Characteristics and applications of a 0.6 μm bipolar-CMOS-DMOS technology combining VLSI non-volatile memories,” IEDM, pp. 465-468, 1996.
[3]A. Andreini, C. Contiero, P. Galbiati, “A new integrated silicon gate technology combining bipolar linear, CMOS logic, and DMOS power parts,” IEEE Trans. Electron Devices, vol. 33, no.12, pp. 2025-2030, 1986.
[4]B. Murari, “Smart power technology and the evolution from protective umbrella to complete system,” IEDM, pp. 9-15, 1995.
[5]E.C. Griffith, J.A. Power, S.C. Kelly, P. Elebert, S. Whiston, D. Bain, M. O'Neill, “Characterization and modeling of LDMOS transistors on a 0.6 μm CMOS technology,” ICMTS, pp. 175-180, 2000.
[6]R. Versari, A. Pieracci, S. Manzini, C. Contiero, B. Ricci, “Hot-carrier reliability in submicrometer LDMOS transistors,” IEDM, pp. 371-374, 1997.
[7]J. Hao, D. Hahn, “Reduction of hot carrier degradation in high
voltage n-channel LDMOS”, IEEE IIRW, pp. 41, 2016.
[8]J. Hao, “Hot carrier reliability in LDMOS devices”, IEEE 12th Int. Conf. ASIC (ASICON), pp. 658-661, 2017.
[9]M. Amato and V. Rumennik, “Comparison of lateral and vertical DMOS specific on-resistance”, in Proc. IEDM, pp. 736–739, 1985.
[10]T. Efland, et al., “An optimized RESURF LDMOS power device module compatible with advanced logic processes”, in Proc. IEDM, pp237-240, 1992.
[11]B. J. Baliga, “Semiconductors for high-voltage, vertical channel FETs”, J. Appl. Phys., vol. 53, pp. 1759-1764, 1982.
[12]W. F. Sun et al., “Hot-carrier-induced on-resistance degradation of n-type lateral DMOS transistor with shallow trench isolation for high-side application”, IEEE Trans. Device Mater. Rel., vol. 15, no. 3, pp. 458-460, Sep. 2015.
[13]J. A. Appels and H. M. J. Vaes, “High voltage thin layer devices (RESURF devices)”, in Proc. IEDM, p. 238, 1979.
[14]A. Ludikhuize, “A review of RESURF technology”, in Proc. IEEE ISPSD, pp. 11–18, 2000.
[15]M. Imam, M. Quddus, J. Adams, Z. Hossain, “Efficacy of charge sharing in reshaping the surface electric field in high-voltage lateral RESURF devices,” IEEE Trans. Electron Devices, vol. 51, no. 1, pp. 141-148, 2004.
[16]B.J. Baliga, Fundamentals of Power Semiconductor Devices, Springer, 2008.
[17]A.Q. Huang, “New Unipolar Switching Power Device Figures of Merit,” IEEE Electron Device Lett., vol. 25, pp 298-301, 2004.
[18]F.-T. Chien, C.-N. Liao and Y.-T. Tsai, “High performance power mosfets by wing-cell structure design,” IEICE Trans. Electron., vol. E89-C, no. 5, pp. 591-595, 2006.
[19]TOSHIBA, Power MOSFET Electrical Characteristics Application Note, 2018.
[20]C.M. Hu, C. Tam, F.C. Hsu, P.K. Ko, T.Y. Chan, K.W. Terrill, “Hot-electron-induced MOSFET degradation model, monitor, and improvement,” IEEE Journal of Solid-State Circuits, vol. 20, no. 1, pp. 295-305, 1985.
[21]P. Hower and S. Pendharkar, “Short and long term safe operating considerations in LDMOS transistors,” Proc. Int. Symp. Power Semicond. Devices, pp. 545-548, 2005.
[22]K. M. Wu, J. F. Chen, Y. K. Su, J. R. Lee, K. W. Lin, J. R. Shih, et al., “Effect of gate bias on hot-carrier reliability in drain extended metal–oxide–semiconductor transistors,” Appl. Phys. Lett., vol. 89, no. 18, pp. 183522, Nov. 2006.
[23]J. F. Chen, S.-Y. Chen, K.-S. Tian, K.-M. Wu, Y.-K. Su, C. M. Liu, et al., “Effects of drift-region design on the reliability of integrated high-voltage LDMOS transistors,” Proc. Dig. Int. Conf. Integr. Circuit Design Technol., pp. 1-4, 2007.
[24]C. C. Cheng, K. C. Du, T. Wang, T. H. Hsieh, J. T. Tzeng, Y. C. Jong, et al., “Investigation of hot carrier degradation modes in LDMOS by using a novel three-region charge pumping technique,” Proc. IRPS, pp. 334-337, 2006.
[25]J. Chen, K.-S. Tian, S.-Y. Chen, K.-M. Wu and C. Liu, “On-resistance degradation induced by hot-carrier injection in LDMOS transistors with STI in the drift region,” IEEE Electron Device Lett., vol. 29, no. 9, pp. 1071-1073, Sep. 2008.
[26]Synopsys, Sentaurus™ Process User Guide Version L-2016.03, March 2016.
[27]Donald A. Neamen, Semiconductor Physics and Devices : Basic Principles, 4e, McGraw-Hill Science Engineering (US), 2011.
[28]M. Gao, L. Zhu, C. K. Peh, G. W. Ho, “Solar absorber material and system designs for photothermal water vaporization towards clean water and energy production,” Energy Environ. Sci., 2018.
[29]A. Ferrara et al., “The safe operating volume as a general measure for the operating limits of LDMOS transistors,” IEDM Tech. Dig., pp. 6.7.1-6.7.4, Dec. 2013.
[30]Koji Shirai et al, “Ultra-low On-Resistance LDMOS Implementation in 0.13μm CD and BiCD Process Technologies for Analog Power IC's” Proc. Int. Symp. Power Semicond. Devices, pp77-79, 2009.
[31]Ralf Rudolf et al, “Automotive 130 nm Smart-Power-Technology including embedded Flash Functionality” Proc. Int. Symp. Power Semicond. Devices, pp20-23, 2011.
[32]Hsueh-Liang Chou1 et al, “0.18 μm BCD Technology Platform with
Best-in-Class 6 V to 70 V Power MOSFETs” Proc. Int. Symp. Power Semicond. Devices, pp401-404, 2012.
[33]R. Roggero et al, “BCD8sP: An Advanced 0.16 μm Technology Platform with State of the Art Power Devices” Proc. Int. Symp. Power Semicond. Devices, pp361-364, 2013.
[34] H.-L. Liu, Z.-W. Jhou, S.-T. Huang, S.-W. Lin, K.-F. Lin, C.-T. Lee, and C.-C. Wang, “A Novel High-Voltage LDMOS with Shielding Contact Structure for HCI SOA Enhancement”, Proc. Int. Symp. Power Semicond. Devices, pp. 311–314, 2017.
[35]Jun-ichi Matsuda, Jun-ya Kojima, Nobukazu Tsukiji, Masataka Kamiya, and Haruo Kobayashi, “Low Switching Loss and Scalable 20-40 V LDMOS Transistors with Low Specific On-Resistance,” International Conference on Technology and Social Science (ICTSS), Apr. 18-20, Kiryu, Japan, I03-02, 2018.
[36]P. Moens, G.V. den bosch, G. Groeseneken, “Hot-carrier degradation phenomena in lateral and vertical DMOS transistors,” IEEE Trans. Electron Devices, vol. 51, no. 4, pp. 623-628, 2004.
[37]C.T. Kirk, “A theory of transistor cutoff frequency (fr) falloff at high current densities,” IEEE Trans. Electron Devices, vol. 9, no. 2, pp. 164-174, 1962.
[38]S. Teja, M. Bhoir and N. R. Mohapatra, “Split-gate architecture for higher breakdown voltage in STI based LDMOS transistors,” 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 1-2, 2017.