碳化矽(SiC)功率元件漸漸使用在各種功率電子應用，碳化矽二極體與金氧半場效電晶體已商業化，並且進入特定的商業市場，同時近年來試圖將碳化矽元件做單晶片整合，特別是應用在極端與惡劣環境下，碳化矽有其優勢。
本論文以4H-SiC為材料，探討1.2kV垂直型雙重離子注入金氧半場效電晶體(DMOS)在使用相同製程下整合水平型互補式金氧半場效電晶體(CMOS)邏輯電路的可能性，實驗結果顯示4H-SiC DMOS在不增加而外光罩下可以兼容整合CMOS邏輯電路，並且反向器與環型振盪器可以利用自身結構隔離耐高壓，NMOS、PMOS、CMOS、ring oscillator在175℃下特性良好，同時發現基板高壓會產生基體效應(body effect)影響PMOS與CMOS電性，但他們仍能正常操作在基板電壓800V時，ring oscillator也能操作在基板300V時，這些結果有望在4H-SiC中整合垂直型DMOS與水平型CMOS邏輯電路。
此外本論文也研究了水平型互補式金氧半導體與橫向擴散金屬氧化物半導體(LDMOS)整合在同一塊基板上，為了整合閘極驅動電路與600V功率MOSFETs，因此量測並探討低壓邏輯電路特性與高壓隔離結構的特性。

4H-silicon carbide (SiC) power components are gradually being used in various power electronic applications. SiC diodes and MOSFETs have been commercialized and entered specific commercial markets. In recent years, attempts have been made to integrate SiC components into a single chip, especially used in extreme and harsh environments where SiC has its advantages.
In this thesis 4H-SiC is used as the semiconductor material to explore possibility of integrating 1.2 kV vertical DMOS with horizontal CMOS logics with the same process technology. The experimental results show that CMOS logic circuits can be compatible and integrated with 4H-SiC DMOS without increasing the number of mask layers, and the inverter and ring oscillator can withstand high voltage using self-isolation. NMOS, PMOS, CMOS, and ring oscillator all have functional characteristics at 175°C. It is found that high substrate voltage will produce body effects that affect the electrical properties of PMOS and CMOS, but they can still operate at a substrate voltage of 800V. The ring oscillator can also operate at a substrate voltage of 300V. These results are promising for integration of vertical DMOS and CMOS logics in 4H-SiC.
In addition, this paper also studies the integration of CMOS and LDMOS on the same substrate in order to realize a gate driver circuit for 600 V power MOSFETs. The characteristics of low-voltage circuit operation and high-voltage isolation structures are measured and discussed.

摘要 i
Abstract ii
目錄 iii
圖目錄 v
表目錄 viii
第一章 序論 9
1.1 前言 9
1.2 碳化矽材料結構 10
1.3 文獻回顧 11
1.3.1 SiC CMOS閘極驅動電路 11
1.3.2 HSPICE BSIM4、BSIM3V3模型 12
1.3.3 Floating guard ring 14
1.3.4 基板的偏壓效應 15
1.4 論文動機與大綱 17
第二章 邏輯電路與LDMOS使用相同基板整合 18
2.1 實驗動機 18
2.2 實驗條件 19
2.2.1 基板結構 19
2.2.2 元件結構 19
2.3 模擬結果 21
2.3.1 前導實驗數據 21
2.3.2 SPICE元件模型建立 22
2.3.3 HSPICE SiC CMOS logic模擬 30
2.3.4 HSPICE SiC N-logic模擬 35
2.4 量測結果與分析 41
2.4.1 製程流程變異 41
2.4.2 I-V curve 42
2.4.3 邏輯電路特性 47
2.4.4 高壓隔離結構結果與討論 53
第三章 水平型CMOS邏輯電路與垂直型DMOS使用相同製程下整合 57
3.1 元件結構與設計 57
3.2 量測結果與分析 58
3.2.1 MOSFETs I-V curve 58
3.2.2 邏輯電路特性 61
3.2.3 基體效應對元件特性量測 69
第四章 結論及未來展望 75
參考文獻 76

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