雖然SiC擁有優越的材料特性，但是SiC MOSFETs仍然面臨著低通道電子遷移率的問題，導致有較高的導通電阻。主要原因為當碳化矽藉由熱氧化製程形成SiO2過程中，部分C原子會堆積在界面處形成缺陷，導致SiC MOS元件會有較高的界面能態密度DIT影響導通特性。為了解決這個問題，一般會使用NO、N2O進行氧化後退火來降低DIT。本論文利用全面性Si離子佈植技術於SiC表面，希望藉由表面的Si離子與非晶態的碳化矽晶體來改善氧化製程，減少界面處C原子相關的缺陷並降低DIT。為了探討Si離子佈植對MOS元件的影響，本論文會使用nMOSCap、LV-nMOSFET與1.2kV的VDMOS來評估元件特性，例如VTH、S.S.、通道電子遷移率、DIT等隨離子佈植劑量的變化，也對VDMOS的崩潰特性作討論，並且利用EDX與XPS量測來分析氧化層界面的材料特性。最後討論Si離子佈植對閘極氧化層可靠度的影響，例如Hysteresis、BTI以及TDDB，也評估了在高壓脈衝量測下，VDMOS於高達1.2kV的動態RON特性。

Although SiC has superior material characteristics, SiC MOSFETs still face the issue of low channel mobility, resulting in high channel resistance. The main reason is that when thermal oxidation process is utilized for SiC to form SiO2, some of the C atoms will accumulate at the interface and form defects, which makes the SiC MOS devices have a high interface state density DIT that affects the conduction characteristics. In order to address these problems, NO and N2O are generally used for post-oxidation annealing to decrease DIT.
This paper uses a blanket Si implantation technique on the SiC surface, aiming to improve the oxidation process by means of introducing Si ions and amorphouszing SiC crystal, possibly reducing C related defects at interface and decreasing DIT. In order to explore the effects of Si implantation on the MOS devices, this paper uses nMOSCap, LV-nMOSFET and 1.2kV VDMOS to evaluate the performance, such as VTH, S.S., channel mobility, and DIT with various implantation doses. In addition, breakdown characteristics of the VDMOS are also discussed, and the material properties of the interface are analyzed using EDX and XPS measurements. Finally, the influence of Si implantation on the reliability of the gate oxide is discussed, such as Hysteresis, BTI, and TDDB. The dynamic RON under a high voltage pulse up to 1.2kV are also evaluated for VDMOS.

中文摘要 II
Abstract III
目錄 V
圖目錄 VIII
表目錄 XIII
第一章 序論 1
1.1 碳化矽材料特性介紹 1
1.1.1 碳化矽材料組成 1
1.1.2 碳化矽的氧化層界面特性 2
1.2 文獻回顧 3
1.2.1 改善SiC/SiO2界面特性與通道遷移率 3
1.2.2 碳化矽MOS元件閘極可靠度-VTH的不穩定性 6
1.2.3 碳化矽MOS元件閘極可靠度-TDDB 8
1.3 研究動機 11
1.4 論文大綱 12
第二章 元件介紹與實驗設計 13
2.1 元件介紹 13
2.1.1 垂直型電容器(MOSCaps) 13
2.1.2 水平型金氧半場效電晶體(Lateral MOSFETs) 14
2.1.3 垂直型雙佈植金氧半場效電晶體(VDMOS) 16
2.2 Si離子佈植 18
2.3 元件特性量測 20
2.3.1 電容-電壓量測(C-V) 20
2.3.2 SiC/SiO2界面能態密度(DIT)電性分析 23
2.3.3 MOSFET順向導通特性 28
2.4 元件閘極可靠度-TDDB 30
2.4.1 Time-to-breakdown, tBD定義 30
2.4.2 統計與數據分析 33
2.4.3 Lifetime的推算 35
第三章 Si離子佈植對元件的影響 38
3.1 WAT量測結果 : epi-layer濃度/厚度 38
3.2 垂直型電容器量測及討論 38
3.3 水平型金氧半場效電晶體量測及討論 43
3.3.1 順向電流量測 43
3.3.2 閾值電壓的變化 47
3.3.3 SiC/SiO2界面的材料分析 48
3.4 垂直型雙佈植金氧半場效電晶體之應用 51
第四章 元件的可靠度 55
4.1 VTH的不穩定性 55
4.1.1 VTH Hysteresis現象 55
4.1.2 BTI的評估 62
4.2 VDMOS RON 的穩定性 68
4.3 nMOSCap TDDB量測結果 70
第五章 氧化層的漏電機制探討 72
5.1 氧化層IG-VGS與步階應力特性 72
5.2 碰撞游離的驗證 76
5.3 檢驗Si離子佈植在兩種漏電機制的差異 81
第六章 結論以及未來展望 82
參考文獻 84

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