可靠度與輻射效應對積體電路(IC)元件是很重要的研究課題。因為在IC元件製造中的電漿製程及EUV微影技術，或是元件應用於航太科技、或衛星通訊都可能處在高能輻射的環境中。高介電係數材料(high-k)閘極已為先進IC元件所使用，因此閘介層的可靠度與輻射傷害值得探討研究。
本論文第一部份，透過不同通道結構來改善電晶體電特性，可以克服短通道效應所造成的問題。對平面式、鰭式以及全環繞式電晶體，經不同輻射傷害後，對元件之電性與可靠度分析。由電晶體電特性的比較，全環繞式電晶體相較於平面式電晶體與鰭式電晶體，有較佳的抗輻射能力。
為了將摩爾定律進一步擴展到5nm以下的技術節點，將鍺材料用於取代矽被視為一種前瞻的解決方案。其不僅擁有比矽更高的載子遷移律，製程技術更與傳統矽製程相容。然而，鍺電晶體的界面品質較差將是其發展的瓶頸。本論文第二部份，探討金屬閘極與high-K閘介電層之界面製程對鍺電晶體電性之影響。High-K氧化層與金屬閘之間以原子層沉積(ALD)成長TiN，來減少界面缺陷、抑制漏電流，可以獲得較佳的元件及抗輻射特性。
第三部份，應用超臨界流體處理來鈍化原子層沉積的閘極介電層，通過SC CO2將H2O分子帶入氧化物薄膜中，並且添加乙醇來增強反應。SC CO2+H2O+乙醇的處理可減少閘極介電層中的缺陷，提升電晶體之電特性。
最後，透過電荷汲引技術(Charge Pumping technique)，探討超臨界流體製程處理的鍺電晶體在經NBTI stress及輻射照射後，對於界面態陷阱(Nit, interface trap)與氧化層陷阱(Not, oxide traps)之影響。因SC CO2+H2O+乙醇的處理可以減少閘極介電層中的缺陷，使元件經輻射照射後有較少的界面陷阱產生，可以獲得較佳的元件及抗輻射特性。

Reliability and radiation effects are very important research topics for integrated circuit (IC) devices, because the IC devices may be in a high-energy radiation environment when a plasma process or EUV lithography are used in IC production, or IC devices are applied in aerospace or satellite communications. Since high-k gate dielectrics are widely implemented in modern IC, the reliability and radiation damage on them are worthy of study.
In the first part of this thesis, the short channel effects of field effect transistor (FET) are reduced and electrical characteristics can be improved by modifying channel structure. The effects of radiation damages on electrical characteristics and reliability of MOSFET, FinFET, and GAAFET were studied. Based on the comparison of electrical characteristics, GAAFET shows better radiation hardness than FinFET and planar MOSFET.
In order to further extend Moore’s law beyond sub-5nm node, Ge is regarded as a promising channel material to replace Si because of not only its much higher carrier mobility but also the compatibility with Si manufacturing technology. However, the poor interface quality of Ge MOSFET is the bottleneck for its development. In the second part of this thesis, the process integration of metal gate/high-k gate dielectric for improving radiation hardness of Ge MOSFET was investigated. The electrical characteristics and radiation hardness of Ge MOSFET can be clearly improved by using an atomic layer deposition (ALD)-formed TiN between high-k gate dielectric and metal gate to decrease the border trap and reduce the leakage.
In the third part of this thesis, a supercritical fluid (SCF) treatment was applied to passivate the ALD formed-gate oxide. The H2O molecules are carried into the oxide film by SC CO2, and the reaction can be enhanced by adding ethanol. The defects in gate dielectric can be reduced and the electrical characteristics of Ge MOSFET can be clearly improved by a SC CO2+H2O+ethanol treatment.
Finally, a charge pumping technique was used to assess the negative bias temperature instability stress and radiation exposure induced oxide and interface traps in Ge MOSFET with SCF treatment. The electrical characteristics and radiation hardness of Ge MOSFET can be clearly improved by a SCF treatment with SC CO2+H2O+ethanol, because the defects in gate dielectric may be reduced.

摘要 i
Abstract iii
致謝 v
目錄 vi
圖目錄 x
表目錄 xv
第1章 序論 1
1.1 前言 1
1.2 使用鍺基板作為通道材料 2
1.3 使用高介電係數材料作為閘極氧化物 3
1.4 鰭式電晶體( FinFET)、全環繞式電晶體(GAAFET) 4
1.5 輻射傷害 4
1.6 論文架構 5
第2章 MOSFET元件在輻射監測之應用研究 11
2.1 金氧半場效電晶體元件與輻射效應 11
2.1.1 MOSFET應用在伽馬輻射劑量計之文獻回顧 12
2.1.2 氧化層電荷和界面陷阱 13
2.2 金氧半場效電晶體之電性量測 14
2.2.1 四點量測電流-電壓(I-V)特性曲線 15
2.2.2 電容-電壓(C-V)特性量測與模擬 15
2.3 負偏壓溫度不穩定效應(NBTI) 15
2.4 電荷汲引技術 17
2.4.1 電荷汲引的方式及原理 17
2.4.2 電荷汲引電流量測裝置及設定 18
2.4.3 邊緣陷阱密度縱深分佈的量測 19
2.5 電荷分離技術的方式與原理 20
2.5.1 利用電荷分離量測電晶體受到電應力所造成損害 20
第3章 平面、鰭式、全環繞式電晶體經輻射傷害之可靠度研究 32
3.1 研究動機 32
3.2 製程與量測 33
3.2.1 製程條件 33
3.2.2 量測參數 34
3.3 平面、鰭式、全環繞式電晶體之電特性分析 34
3.3.1 電流-電壓量測 34
3.3.2 FN Stress量測 35
3.4 平面、鰭式、全環繞式電晶體經輻射照射後之電特性分析 35
3.4.1 電流-電壓量測 35
3.5 結論 37
第4章 原子層沉積金屬閘電極在鍺電晶體經輻射傷害之可靠度研究 50
4.1 研究動機 50
4.2 製程與量測 51
4.2.1 製程條件 51
4.2.2 量測參數 52
4.3 原子層沉積金屬閘電極在純鍺電晶體之電特性分析 52
4.3.1 電流-電壓量測 52
4.3.2 電容量測 53
4.3.3 閘極漏電流密度對電壓量測 53
4.4 原子層沉積金屬閘電極在純鍺電晶體經輻射照射後之電特性分析 54
4.4.1 電流-電壓量測 54
4.5 FN Stress與輻射損傷之探討 55
4.6 結論 56
第5章 應用超臨界流體處理閘極氧化層對鍺電晶體之可靠度研究 73
5.1 研究動機 73
5.2 製程與量測 74
5.2.1 製程條件 74
5.2.2 量測參數 74
5.3 應用超臨界流體處理閘極氧化層對鍺電晶體之電特性分析 75
5.3.1 電容量測 75
5.3.2 閘極漏電流密度對電壓量測 75
5.3.3 電流-電壓量測 76
5.4 NBTI stress量測 76
5.5 元件壽命預測 78
5.6 結論 78
第6章 電荷汲引技術應用於超臨界流體處理閘極氧化層對鍺電晶體 104
6.1 研究動機 104
6.2 電荷汲引技術 105
6.2.1 量測方法 105
6.3 量測結果與討論 107
6.3.1 電荷汲引電流 107
6.3.2 利用電荷汲引技術分析鍺電晶體經NBTI stress後之退化機制 107
6.4 應用超臨界流體處理閘極氧化層對鍺電晶體經輻射照射之電特性分 109
6.4.1 電流-電壓量測 109
6.4.2 電荷汲引電流 109
6.5 結論 110
第7章 結論 130
參考文獻 131

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