過去，因為CMOS製程操作頻率的限制，毫米波電路大多使用三五族元素的元件製作，但三五族元素的元件成本比較高，使毫米波電路普及受到限制。隨著半導體製程的發展，縮小電晶體的尺寸同時也提高了其操作頻率，提升了CMOS製程製作毫米波電路的可能性。相比於三五族製程，CMOS擁有較高的整合性和較低的成本，使毫米波電路更加普及。而在毫米波系統中，鎖相迴路扮演了一個很重要的角色，廣泛應用於現今的通訊系統，除此之外，更可應用於時脈資料回復及影像感測系統。
本論文探討了鎖相迴路之中的子電路，主要分為震盪器和除頻器。第一個設計為操作在W-Band的壓控震盪器，利用台積電90奈米互補式金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor, CMOS)製程實現。調頻範圍為6.43%，在1 MHz和 10 MHz 的相位雜訊分別為-77.7 dBc/Hz 和 -110.1 dBc/Hz，含輸出緩衝器總共消耗30.36 mW。第二個設計為操作在300-GHz 的二倍頻諧波震盪器，在288.5-GHz得到-12.8 dBm的輸出功率，消耗 21.5 mW，利用台積電40奈米互補式金屬氧化物半導體製程實現。第三個設計為操作在150 GHz的注入鎖定除二除頻器，在-10 dBm的輸入功率下，得到152.49~157.73 GHz的鎖定範圍，總共消耗5.8 mW，使用台積電40奈米互補式金屬氧化物半導體製程實現。

In the past, millimeter wave circuits were usually utilized by III-V semi-conductor technologies because of the operation frequency limitation of CMOS process. But, the cost of III-V semi-conductors is relatively high, which leads to limited popularity of the millimeter-wave circuits. With the development of semi-conductor process, the gate length of CMOS transistor becomes smaller and the operation frequency increases in the meantime, facilitating the possibility of CMOS millimeter-wave circuits. Compared to III-V semi-conductor process, the higher integration capacity and lower cost of CMOS process make millimeter wave circuits more popular. In millimeter-wave systems, phase-locked loop (PLL) plays an important role. In addition to communication systems, PLLs are critical in image sensor systems and Clock and Data Recovery (CDR) circuit.
In this thesis, the critical circuit in PLLs are discussed, mainly the voltage-controlled oscillator (VCO) and the frequency divider. The first design is a VCO operating in W-band in tsmc 90-nm CMOS with 6.43% frequency tuning range. The phase noise are -77.7-dBc/Hz at 1-MHz and -110.1-dBc/Hz at 10-MHz, respectively. The dc power is 30.36 mW including that of the output buffers. The second design is a push-push oscillator operating at 300 GHz in tsmc 40-nm CMOS technology. The output power at 288.5 GHz is -12.8 dBm. The dc power dissipation is 21.5 mW. The last design is a divided-by-two Injection-Locked Frequency Divider (ILFD) operating at 150 GHz implemented in tsmc 40-nm CMOS technology. With -10 dBm input power, the locking range is from 152.49 GHz to 157.73 GHz and the power dissipation is 5.8 mW.

摘要 i
ABSTRACT ii
Contents iii
List of Figures vi
List of Tables xi
Chapter 1 Introduction 1
1.1. Background 1
1.2. Organization 2
Chapter 2 Overview of Phase-Locked Loop 3
2.1. Introduction 3
2.2. System Models of PLL 6
2.2.1 PLL with First-order Loop Filter 6
2.2.2 PLL with Second-order Loop Filter 11
2.2.3 Noise in PLLs 14
2.3. LC-Tank VCO 19
2.3.1 Introduction 19
2.3.2 Specifications of VCO 22
2.3.2.1 Tuning Range 22
2.3.2.2 Phase Noise 23
Chapter 3 A W-Band VCO with LC Source Degeneration in 90-nm CMOS 24
3.1. Introduction 24
3.2. LC Source Degeneration 25
3.3. Varactors and Body-Bias Technique 28
3.4. Proposed Circuit 31
3.5. Simulation and Measurement Results 33
3.6. Discussion and Conclusion 36
Chapter 4 A 300-GHz Phase-locked Loop in 40-nm CMOS 38
4.1. Overall Circuit Architecture 38
4.2. A 300-GHz Transformer-Based Oscillator 39
4.2.1 Introduction 39
4.2.2 Transformer-Based Resonator 40
4.2.3 Maximum Output Power of Harmonic Oscillators 42
4.2.4 Proposed Circuit 46
4.2.5 Simulation and Measurement Results 54
4.2.6 Discussion and Conclusion 58
4.3. A 150-GHz Injection-Locked Frequency Divider 62
4.3.1 Introduction 62
4.3.2 Analysis of Injection-locked Frequency Divider 64
4.3.3 Proposed Circuit 68
4.3.4 Simulation and Measurement Results 72
4.3.5 Discussion and Conclusion 76
4.4. System Consideration 78
4.4.1 Loop Bandwidth Design 78
4.4.2 Experiment Results 80
Chapter 5 Conclusion and Future Work 83
Reference 85

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