近年來，在半導體製程技術不斷演進的過程中，金氧半場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET)元件尺寸不斷微縮，傳統平面式MOSFET此時在微縮過程中遇到了瓶頸，加州大學伯克利分校胡正明教授發明了鰭式場效電晶體(Fin Field-Effect Transistor, FinFET)被視為在20奈米製程下主要解決方法，更在2011年後廣泛運用於市面產品中。
然而在先進CMOS製程中，最重要的挑戰就是精確的控制3D結構而達成奈米微縮(nano-scale)。隨著閘極氧化層厚度越來越薄，氧化層可靠度與氧化層高介電材料也是微縮製程中之重要考量之一，因此確實的偵測及預防因為電晶體微縮而越來越嚴重的電漿充電效應更加重要。
之前的研究利用FinFET製程提出了一個新型的電漿感應電荷偵測器結構，成功的紀錄在後端製程上電漿電荷累積的程度，此電漿感應電荷偵測器擁有天線耦合浮動閘極，吸引基板的電荷進出浮動閘極。量測到的臨界電壓值可以推出浮動閘極電荷和電場，進而預測出作用於電晶體閘極上的真實電壓分佈，對於未來的FinFET製程最佳化和可靠性評估有極大的幫助。
這篇論文利用FinFET製程延續了之前的研究，提出了新的測試模型，用於評估電漿充電效應對緊密放置的金屬線之間電介質層完整性的影響，並全面分析了電漿離子充電強度與在IMD層中發現之損傷之間的相關性，以及在新型的電漿感應電荷偵測器旁邊加上不同種類與大小的電容，使得新型的PID紀錄器可偵測到的電漿充電強度範圍更廣，更加確信了新型的電漿感應電荷偵測器能完整地量測出後端製程上電漿電荷的影響，有助於半導體業界未來的產能與良率的提升。

In recent years, during the continuous evolution of semiconductor process technology, the size of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices has continued to scale down. The traditional planar MOSFET encountered a bottleneck during the miniaturization process. Professor Zheng-ming Hu of the University of California, Berkeley, invented the FinField-effect transistor (FinFET), which is regarded as the main solution beyond the 20nm technology node, and has been widely adapted by the industry since 2011.
In the advanced CMOS technology, one of the key challenge is to accurately control the 3D structure to achieve nano-scale transistors. As the gate dieletric layer becomes thinner and thinner, the reliability of the metal gate and the high-k dielectric layers remains the major concerned in the development of 3D transistors. Therefore, we need more accurate detection and prevention of serious plasma induced damage due to miniaturization.
The previous research used the FinFET process to propose a novel Plasma Induced Damage (PID) detector structure, which successfully recorded the plasma charging levels on the back-end process. The PID detector has an antenna-coupled floating gate to attract the charge of the substrate into and out of the floating gate. The measured threshold voltage value can deduce the floating gate charge and electric field, and then predict the true voltage distribution acting on the transistor gate, which will greatly help the optimization and reliability evaluations of FinFET processes in the future.
In advanced CMOS FinFET technologies, tightly packed interconnect layers are expected to cause reliability concerns on inter metal dielectric (IMD) layers. In this study, two newly designed test patterns are used to investigate the plasma induced charging effect on the integrity of IMD films. Experimental data demonstrate that there are strong correlations between the plasma charging levels and damages found in IMD layers.
Newly proposed on-wafer test patterns for assessing wide-range plasma induced charging levels in advanced FinFET logic processes have been demonstrated. By sizing up the capacitor linked to the antenna node, the maximum sensing level can be extended successfully.

摘要 1
Abstract 2
致謝 4
內文目錄 5
附圖目錄 7
附表目錄 9
第一章 序論 10
1.1 電漿充電效應簡介 10
1.2 研究動機 12
1.3 論文大綱 13
第二章 電漿充電效應紀錄元件介紹與操作 17
2.1 元件結構 17
2.2 載子注入機制回顧 18
2.3 耦合結構設計 19
2.4 元件操作機制 20
2.5 小結 21
第三章 金屬間介電質之電漿充電效應 30
3.1 量測裝置及機台設定 31
3.2 金屬間介電質設計 32
3.3 基本特性量測 33
3.4 單向電荷與雙向電荷比較 34
3.5 金屬間介電層之電漿充電效應晶圓圖上強度分佈 35
3.6 小結 35
第四章 外加電容效應分析 47
4.1 外加電容設計 48
4.2 基本特性量測 49
4.3 外加電容紀錄元件之成效分析 49
4.4 外加電容紀錄元件之推導 50
4.5 小結 51
第五章 參考元件臨界電壓變異性 64
5.1 臨界電壓與次臨界擺幅定義 64
5.2 蒙地卡羅模擬法參數設置 66
5.3 蒙地卡羅模擬法結果分析 67
5.4 小結 68
第六章 總結 76
6.1 元件與現行偵測方法之比較 76
6.2 結語與未來展望 77
參考文獻 78

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