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作者(中文):蔡昀廷
作者(外文):Tsai, Yun-Ting
論文名稱(中文):標準CMOS製程中橫向NPN電晶體於高動態範圍影像偵測器之應用
論文名稱(外文):Application of the Lateral NPN Transistor in 0.18 μm Standard CMOS Technology to High Dynamic Range Image Sensor
指導教授(中文):徐永珍
指導教授(外文):Hsu, Klaus Yung-Jane
口試委員(中文):江雨龍
賴宇紳
口試委員(外文):Jiang, Yue-Long
Lai, Yu-Sheng
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學號:107063528
出版年(民國):110
畢業學年度:109
語文別:中文
論文頁數:72
中文關鍵詞:標準製程影像感測器橫向式電晶體高響應度高動態範圍光偵測器
外文關鍵詞:standard cmos technologyimage sensorlateral phototransistorhigh dynamic rangehigh responsivityphotodetector
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近年來隨著科技的日新月異,影像感測器在人們的生活扮演了舉足輕重的角色。目前市面上的影像感測器在低光源與高動態範圍下的影像處理大多仰賴後續的軟體整合,而本研究之目的是在不更動任何現有製程條件下,以TSMC標準製程製作出具有高響應度的橫向式光電晶體作為影像感測器像素中的感光元件,並搭配本論文之高動態範圍之像素陣列、結合二次相關取樣電路以消除雜訊與暗訊號,且將數位訊號之生成電路與偏壓電路整合於一片晶片之中。
本研究使用標準的TSMC 0.18 μm 1P6M Standard CMOS製程做整合,實際下線晶片影像陣列為64×48陣列。利用純矽製程製作出高響應度之橫向式光電晶體嘗試實踐一個具有高動態偵測範圍之影像感測系統,相較於過去實驗室所實踐之建構於Bi-CMOS製程下的晶片系統,本研究具有較低的成本,對於可商品化來說是一大優勢。
晶片本身並未封裝,面積包含Pads為3.305 mm2,外接專門設計之PCB板進行量測。量測結果發現,由於佈局時並未妥善考量走線上數位訊號與類比訊號之間過於靠近或交錯會造成輸入基頻訊號對類比輸出訊號產生干擾。本次電路應用確實能在輸入基頻的控制下依序將訊號傳出,但受限於佈局疏失無法有效實現橫向式電晶體在影像感測器上的表現。
Recently, image sensors played a decisive role in human’s life as technology has had a rapid progress. Currently, most image sensors on the market rely on rear end image processing by software engineering when dealing with low light and high-contrast images. In this thesis, my goal is to make a lateral phototransistor (LPT) with high responsivity and use it as the photodetector in the image sensing array without any process modifications. The high dynamic range 64×48 pixel array with the embedded LPT’s was integrated with a digital circuit, a bias circuit, and a correlated double sampling circuit which is designed to eliminate fixed-pattern noise and dark signals.
The image sensor with a 64×48 pixel array was fabricated with the TSMC 0.18 μm 1P6M Standard CMOS technology. Using the pure CMOS technology to implement a high dynamic range image sensing system has an obvious cost advantage for commercialization when compared with using the 0.18 μm Standard SiGe BiCMOS technology adopted by our laboratory previously.
The area of the sample chip is 3.305 mm2 and it is not packaged. A specific PCB board was designed to finish the measurements. According to the measurement, input clock signal produces interferences to the output signal due to my lack of consideration during layout. The metal lines of digital signals and analog signals, which are too close or cross each other, would cause bad influence to the chip. In this design, we indeed observed the sequential output signal under the control of input clock and digital circuit. Nevertheless, the performance of lateral phototransistors on image sensors could not be observed effectively due to the interferences.
目錄
摘要 I
Abstract II
致謝 III
目錄 IV
圖目錄 VII
表目錄 X
第一章 前言 1
1.1 影像感測電路的發展及應用 1
1.2 研究動機 4
1.3 論文章節架構 5
第二章 CMOS影像感測器之基本特性 6
2.1 CMOS影像感測器之操作與原理 6
2.2 CMOS影像感測器的特性與參數 7
2.2.1 量子效率(Quantum efficiency)與響應度(Responsivity) 7
2.2.2 響應時間(Response time) 8
2.2.3 填充係數(Fill Factor) 9
2.2.4 吸收係數(Absorption Coefficient) 10
2.2.5 暗電流(Dark Current) 11
2.2.6 動態範圍(Dynamic Range) 11
2.2.7 畫面速率 (Frame Rate) 11
2.2.8 雜訊(Noise) 12
2.3 CMOS影像感測器常見之像素結構 13
2.3.1 被動式像素感測器CMOS(Passive Pixel Sensor, PPS) 13
2.3.2 主動式像素感測(Active Pixel Sensor, APS) 13
2.3.3 數位式像素感測(Digital Pixel Sensor, DPS) 16
2.4 常見抑制CMOS影像感測器雜訊之讀出電路 17
第三章 電路設計 18
3.1 橫向式光電晶體原理 19
3.2 像素電路原理 27
3.3 相關二次取樣電路設計原理 31
3.3.1 工作原理 32
3.3.2 各元件之尺寸 34
3.4 輸出緩衝器(Output buffer)設計原理 35
3.5 偏壓電路設計原理 37
3.6 數位電路設計原理 39
第四章 模擬結果 44
4.1 經過源極追隨器之訊號之模擬 44
4.2 輸出之訊號之模擬 45
4.3 晶片布局 52
4.4 PCB之設計 54
第五章 量測結果與討論 56
5.1 量測儀器簡介 56
5.2 量測系統 57
5.3 量測方式 58
5.3.1 64x48陣列輸出之量測 58
5.4 量測結果 61
5.4.1 單顆像素輸出之量測結果 61
5.4.2 不同輸入頻率輸出結果之比較 62
5.4.3 64x48陣列輸出之量測結果 63
5.4.4 結果分析與討論 65
第六章 結論與未來展望 68
6.1 結論 68
6.2 未來展望 69
參考文獻 70

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