這篇論文在闡述一種類比數位轉換器，轉換器的規格要求為12位元且取樣頻率為10 MHz，在架構上採用的是1階段連續漸進式類比數位轉換器，然而連續漸進式轉換器最主要的缺點就是電容佔了太多的面積，因此利用了passive noise shaping的方式在9 bit CDAC的結構上實施雜訊重塑，有效提升ADC的ENOB到12 bit，不只比結構上全部用SAR做更能降低功耗，也更省面積。

這個架構是在TSMC 0.18 um 1P6M CMOS製程下給予實現，晶片總面積包含TSMC 的ESD I/O pad為1.88mm2，若是僅core 面積為0.58mm2，此類比數位轉換器的供應電壓為1.8V、取樣頻率10 MHz，訊號背景為輸入146.484375 kHz的正弦波，訊號對雜訊及失真比（SNDR）以及有效位元數（ENOB）的模擬結果分別是73.97 dB以及11.99，而平均功耗的結果為1.288mW，分析DNL及INL的靜態模擬結果分別為（1.15 / -1 LSB）以及（1.05 / -0.53 LSB）。

This paper presents an analog-to-digital converter (ADC). The design specifications of the converter are 12-bit effective number of bits (ENOB) and 10 MHz sampling frequency. The architecture of the ADC is based on a one-stage successive approximation register (SAR) analog-to-digital converter. Conventionally, the main disadvantage of the SAR ADC is that the capacitors in the converter occupy too much area. Therefore, we use the passive noise shaping method to perform noise reshaping on the 9-bit capacitive digital-to-analog converter (CDAC) in the SAR ADC, which increases the ENOB of the ADC to 12 bits. This approach reduces much power and area.
This structure is implemented under the TSMC 0.18 um 1P6M CMOS process. The total chip area, including TSMC’s ESD I/O pads, is 1.88 mm2 and the core circuit occupies 0.58 mm2. The supply voltage of the circuit is 1.8 V, and the sampling frequency is 10 MHz. When a 146.484375-kHz sine wave is used as the input signal, simulation result shows that the signal-to-noise and distortion ratio (SNDR) and the ENOB are 73.97 dB and 11.99 bits, respectively. The average power consumption is 1.288 mW, and the differential nonlinearity (DNL) and integrated nonlinearity (INL) are (1.15 / -1 LSB) and (1.05 / -0.53 LSB), respectively.

目錄
摘要 I
Abstract II
致謝 III
目錄 IV
圖目錄 VI
表目錄 IX
第一章 緒論 1
1.1研究背景 1
1.2 研究動機 2
1.3 論文章節架構 4
第二章 研究介紹與架構說明 5
2.1 ADC參數介紹 5
2.2 ADC電路的架構說明 9
2.2.1 連續漸進式類比數位轉換器(SAR ADC) 9
2.2.2 三角積分類比數位轉換器(Sigma-delta ADC) 12
第三章 將雜訊整形應用在SAR ADC上 15
3.1 取樣定理和量化雜訊 15
3.1.1 奈奎斯特取樣定理(Nyquist theorem) 15
3.1.2 超取樣定理 16
3.1.3 量化雜訊(Quantization noise) 18
3.2 雜訊整形(Noise Shaping)應用在SAR ADC上 22
第四章 電路架構設計與探討 26
4.1 DAC設計與考量 26
4.2 類比數位轉換器設計及其運作原理 28
4.2.1 由S/H 影響DAC切換的流程 28
4.2.2 Noise Shaping流程及考量 29
4.2.3 取樣保持電路(Sample And Hold, S/H) 31
4.2.4 比較器電路(Comparator) 32
4.2.5 非同步控制邏輯電路(Asynchronous control circuit) 33
4.2.6 SAR邏輯電路(SAR Logic Circuit) 34
4.2.7 開關電路 35
4.3 開關的非理想效應 36
4.3.1 電荷注入(charge injection) 36
4.3.2 時脈饋通(clock feedthrough) 37
4.3.3 熱雜訊(thermal noise) 38
第五章 模擬與佈局 39
5.1 Pre-simulation 39
5.1.1 Boostrap電路(S/H)模擬 39
5.1.2 比較器電路(Comparator)模擬 40
5.1.3 總系統電路模擬 42
5.2 晶片布局 44
5.3 Post-simulation 46
5.3.1 Boostrap電路(S/H)模擬 46
5.3.2 比較器電路(Comparator)模擬 47
5.3.3 總系統電路模擬 49
5.4 預計規格表 50
5.5 文獻比較 50
第六章 量測與討論 52
6.1 PCB設計和量測環境設定 52
6.2 量測儀器介紹 55
6.3 量測結果和討論 56
第七章 總結與研究建議 61
7.1 總結 61
7.2 研究建議 62
參考文獻 63

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