現今的計算架構所採用之范紐曼型架構(Von Neumann Architecture)隨著AI人工智慧以及高速計算的要求愈來愈高，面臨著功率消耗大以及資料傳輸速度慢的瓶頸。為了突破此瓶頸，近年來學者們提出將簡單的邏輯運算移至記憶體內，使記憶體內不只儲存資料，還能進行運算，如此便能降低資料傳輸所造成的功率消耗，並能使運算的速度不受資料傳輸速度影響。現今的記憶體中以快閃記憶體(Flash Memory)為主流，然而隨著製程上微縮，快閃記憶體將面臨浮動閘極中儲存電荷減少的問題，也因此，新型態記憶體如相變式記憶體、磁阻式隨機存取記憶體以及電阻式隨機存取記憶體逐漸地受到重視。其中電阻式記憶體具有低功耗、高速操作的優點，適合用於高速運算之整合記憶模組。
本論文以16奈米製程實現一三維可堆疊的雙位元通孔電阻式記憶體鎖存器，此記憶體與邏輯閘混合之電路單元可完全相容於鰭式場效電晶體邏輯製程，不需要額外的光罩以及步驟。利用邏輯製程中後段(Back-end process)通孔與金屬結構所形成的雙位元通孔電阻式記憶體，使三維可堆疊的雙位元通孔電阻式記憶體鎖存器具有高耐用度、高操作速度與高密度運算等特性。藉由量測以及模擬分析，此種鎖存器具有良好的資料保存能力；並且不會因受到干擾而導致輸出錯誤。本研究針對電阻式記憶體元件與元件差異上，提出一鏡像鎖存器，透過鏡像的結構，降低鎖存器內的通孔電阻式記憶體之間之差異。接著利用通孔電阻式記憶體的堆疊特性，在不增加面積的情況下使儲存資料增加，並且達到更多元的運算效果。此種三維可堆疊的雙位元通孔電阻式記憶體鎖存器極可能成為發展新一代高速運算的候選人之一。

Power consumption and data transmission in advanced computing units have become the critical bottlenecks of circuit speed, in recent years. Hence, researches and developments start to seek alternative approaches such as computing-in-memory (CIM) and neural network (NN) based architectures to further boost computational power and efficiency. Resistive random access memory (RRAM), featuring high density and high-compatibility to CMOS technologies, has been one of the promising candidates for realizing future neuromorphic computing systems. The “near-data processing” architecture places logic circuits inside memory to avoid the speed limitations as a result of the von-Neumann bottleneck. However, RRAM-based NN subjects to stability and variability problems which can lead to faulty functions, computational glitches, and reliability concerns. The memristor-based nonvolatile logics has been reported in many prior studies, which typically required special RRAM processes which are not fully compatible to advance CMOS process. In this work, we investigate a non-volatile (NV) logic gate with complementary resistive switches through BEOL Via structures implemented in 16nm FinFET processes. By incorporating the twin-bit RRAM cell, a new memory-logic hybrid gate with full compatibility to FinFET logic processes, superior endurance and stable logic output is demonstrated. Through the unique shared-via arrangement, the twin-pair RRAM forms a complementary latch (CL) to increase immunity to variations and ensure well-controlled logic states during operations.

摘要..........................i
Abstract......................ii
致謝...........................iii
內文目錄.......................iv
附圖目錄.......................vi
附表目錄.......................viii
第一章 序論......................1
1.1 前言........................1
1.2 論文大綱.....................3
第二章 相關技術回顧與發展...........4
2.1 電阻式隨機存取記憶體...........4
2.1.1 電阻式隨機存取記憶體基本結構...........4
2.1.2 初始化......................5
2.1.3 設置/重置與操作極性...........5
2.1.4 電阻式隨機存取記憶體物理模型...........6
2.2 應用電阻式記憶體之非揮發性邏輯閘技術回顧...........7
2.3 FinFET製程下之雙位元通孔電阻式記憶體介紹...........9
2.3.1 雙位元通孔電阻式記憶體元件結構...........9
2.3.2 元件基本特性...........10
2.4 研究動機與目的...........10
第三章 雙位元通孔電阻式記憶體鎖存器...........23
3.1 單層鎖存器結構...........23
3.2 單層鎖存器之操作機制...........24
3.3 單層鎖存器特性量測與模擬結果分析...........25
3.4小結...........27
第四章 鏡像鎖存器...........41
4.1 對位不準與元件變異探討...........41
4.2 鏡像鎖存器結構...........42
4.3 量測與模擬結果分析...........43
4.4 小結...........44
第五章 三維可堆疊鎖存器...........50
5.1 三維可堆疊鎖存器結構...........50
5.2 鎖存器之操作流程...........51
5.3 模擬結果分析...........52
5.4小結...........53
第六章 總結...........60
參考文獻...........62

[1] I. -. Kim et al., "Overcoming DRAM scaling limitations by employing straight recessed channel array transistors with <100> uni-axial and [100] uni-plane channels," IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest., Washington, DC, 2005, pp. 319-322
[2] M. Kim and W. Cho, "Characteristics of Fully Depleted Strained-Silicon-On-Insulator Capacitorless Dynamic Random Access Memory Cells," in IEEE Electron Device Letters, vol. 30, no. 12, pp. 1356-1358, Dec. 2009
[3] C. Sun, K. Han and X. Gong, "Performance Evaluation of Static Random Access Memory (SRAM) based on Negative Capacitance FinFET," 2019 International Conference on IC Design and Technology (ICICDT), SUZHOU, China, 2019, pp. 1-4
[4] C. M. R. Prabhu and A. K. Singh, "Low-power fast static random access memory cell," 2010 International Conference on Computer Applications and Industrial Electronics, Kuala Lumpur, 2010, pp. 5-8
[5] M. Ziegler, R. Günther and H. Kohlstedt, "Complementary Floating Gate Transistors With Memristive Operation Mode," in IEEE Electron Device Letters, vol. 37, no. 2, pp. 186-189, Feb. 2016.
[6] N. M. Hossain and M. H. Chowdhury, "Multilayer graphene nanoribbon floating gate transistor for flash memory," 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, 2014, pp. 806-809.
[7] Y. Chen, X. Wang, H. Li, H. Xi, Y. Yan and W. Zhu, "Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 12, pp. 1724-1734, Dec. 2010.
[8] L. Zhang, X. Fong, C. Chang, Z. H. Kong and K. Roy, "Highly Reliable Spin-Transfer Torque Magnetic RAM-Based Physical Unclonable Function With Multi-Response-Bits Per Cell," in IEEE Transactions on Information Forensics and Security, vol. 10, no. 8, pp. 1630-1642, Aug. 2015.
[9] D. Ventrice, P. Fantini, A. Redaelli, A. Pirovano, A. Benvenuti and F. Pellizzer, "A Phase Change Memory Compact Model for Multilevel Applications," in IEEE Electron Device Letters, vol. 28, no. 11, pp. 973-975, Nov. 2007.
[10] R. Bez, P. Cappelletti, G. Servalli and A. Pirovano, "Phase Change Memories have taken the field," 2013 5th IEEE International Memory Workshop, Monterey, CA, 2013, pp. 13-16.
[11] K. Zhang et al., "Ultra-Low Power Ni/HfO2/TiOx/TiN Resistive Random Access Memory With Sub-30-nA Reset Current," in IEEE Electron Device Letters, vol. 36, no. 10, pp. 1018-1020, Oct. 2015.
[12] P. Chen, Y. Su and F. Chang, "Stabilizing Resistive Switching Characteristics by Inserting Indium-Tin-Oxide Layer as Oxygen Ion Reservoir in HfO2-Based Resistive Random Access Memory," in IEEE Transactions on Electron Devices, vol. 66, no. 3, pp. 1276-1280, March 2019.
[13] J. Backus, “Can Programming Be Liberated from the von Neumann Style? A Functional Style and Its Algebra of Programs,” in Communications of the ACM, Vol. 21, No. 8, August 1998.
[14] P. Chih, S. Li, C. Xu, T. Zhao, Y. Liu, Y. Wang and Y. Xie, “PRIME: A Novel Processing-in-memory Architecture for Neural Network Computation in ReRAM-based Main Memory,” in EEE 43rd Annual International Symposium on Computer Architecture (ISCA), pp. 27–39, June 2016.
[15] Z. Zhao, Y. Wang, X. Zhang, X. Cui and R. Huang, "An Energy-Efficient Computing-in-Memory Neuromorphic System with On-Chip Training," 2019 IEEE Biomedical Circuits and Systems Conference (BioCAS), Nara, Japan, 2019, pp. 1-4.
[16] W. Khwa et al., "A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, 2018, pp. 496-498.
[17] T. Mikolov, M. Karafiat, L. Burget, J. H. Cernocky, and S. Khudanpur, “Recurrent neural network based language model,” 2016 International Conference on Asian Language Processing (IALP), pp. 1045–1048, September 2010.
[18] N. Jin and D. Liu, "Wavelet Basis Function Neural Networks for Sequential Learning," in IEEE Transactions on Neural Networks, vol. 19, no. 3, pp. 523-528, March 2008.
[19] W. Lin and G. Chen, "Large Memory Capacity in Chaotic Artificial Neural Networks: A View of the Anti-Integrable Limit," in IEEE Transactions on Neural Networks, vol. 20, no. 8, pp. 1340-1351, Aug. 2009.
[20] X. Wang, Q. Wang, F. Meng, S. H. Lee and W. D. Lu, "Deep Neural Network Mapping and Performance Analysis on Tiled RRAM Architecture," 2020 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Genova, Italy, 2020, pp. 141-144
[21] T. C. Jackson, A. A. Sharma, J. A. Bain, J. A. Weldon and L. Pileggi, "An RRAM-based Oscillatory Neural Network," 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS), Montevideo, 2015, pp. 1-4
[22] H. -. P. Wong et al., "Metal–Oxide RRAM," in Proceedings of the IEEE, vol. 100, no. 6, pp. 1951-1970, June 2012
[23] Yu-Sheng Chen et al., "Forming-free HfO2 bipolar RRAM device with improved endurance and high speed operation," 2009 International Symposium on VLSI Technology, Systems, and Applications, Hsinchu, 2009, pp. 37-38
[24] U. Russo, D. Ielmini, C. Cagli and A. L. Lacaita, "Self-Accelerated Thermal Dissolution Model for Reset Programming in Unipolar Resistive-Switching Memory (RRAM) Devices," in IEEE Transactions on Electron Devices, vol. 56, no. 2, pp. 193-200, Feb. 2009
[25] P. Huang et al., "A physical based analytic model of RRAM operation for circuit simulation," 2012 International Electron Devices Meeting, San Francisco, CA, 2012, pp. 26.6.1-26.6.4
[26] Z. Yang and L. Wei, "Logic Circuit and Memory Design for In-Memory Computing Applications using Bipolar RRAMs," 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5.
[27] P. Yao et al., "Intelligent Computing with RRAM," 2019 IEEE 11th International Memory Workshop (IMW), Monterey, CA, USA, 2019, pp. 1-4.
[28] X. Cui, Y. Ma, F. Wei and X. Cui, "The Synthesis Method of Logic Circuits based on the NMOS-like RRAM Gates," in IEEE Access
[29] Yung-Wen Chin; Shu-En Chen; Min-Che Hsieh; Tzong-Sheng Chang; Chrong Jung Lin; Ya-Chin King*, “Point twin-bit RRAM in 3D interweaved cross-point array by Cu BEOL process,” in 2014 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2014.
[30] Yi-Hong Shih, Meng-Yin Hsu, Chrong Jung Lin and Ya-Chin King, “Twin-bit Via RRAM in 16nm FinFET Logic Technologies” in 2017 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, Sept. 2017.