近年的科技快速進步，有高偵測率的光偵測器在生活中的應用日漸增加，如何創造出操作電壓小、耗能小以及易於外部電路整合成單一晶片等優點的單光子偵測器，將會是相當有前瞻性的研究，而普遍常見的單光子崩潰二極(Single photon avalanche diode, SPAD)的操作電壓大約在十幾伏特以上，為了使操作電壓可以更少，本論文將嘗試利用電晶體設計單光子崩潰電晶體(Single photon avalanche transistor, SPAT)。
本篇論文的縱向電晶體架構，在不更動任何現有製程條件的情況下，採用TSMC 0.18μm 標準CMOS製程製作。利用電晶體的BVCBO>BVCEO特性，使電晶體操作電壓定為BVCEO。為了操作SPAT，我們詳細探討利用主動冷卻電路(Active quenching circuit, AQC)克服遲滯現象的可能性，除此之外，設計的AQC可調變Hold-off time的功能，可依元件特性調解Hold-off time長度。
量測結果發現，由於操作在Geiger mode，在崩潰的時候，電晶體的響應度確實可以到達30 GA⁄W等級，對於弱光極為敏感。不過，如果要使用於SPAT的應用，須對基極電位設計一個開關，源於發生崩潰時，會有大量的電洞存在於基極端，如果不將其電洞快速排出的話，電子依舊會從射極注入過來，將無法進行下一次的計數。

Along with the rapid improvement of technology, the applications of photodetectors with high sensitivity increase gradually. Creating single-photon avalanche detectors with low bias voltage, low power consumption, and easy integration with quenching circuits can be prospective research. In general, a SPAD is biased at high voltage larger than 10V. In order to reduce operation voltage, a SPAT is designed as a function of a photodetector in this work.
In this work, a vertical transistor with low breakdown voltage is presented by TSMC 0.18μm standard CMOS process without any process modifications. It is biased at BVCEO by taking advantage of the characteristic of a transistor, BVCBO>BVCEO. For the purpose of controlling the SPAT, an AQC is introduced to evaluate the probability of overcoming the hysteresis effect. Furthermore, the AQC is also designed to adjust the hold-off time according to the characteristic of the SPAT.
Measurement shows that the SPAT is operating in Geiger mode and its responsivity can reach 30 GA⁄W. It is extremely sensitive to the low power light. A large number of holes are generated during the avalanche period, and these holes need to be repelled rapidly. Otherwise, it can be difficult to detect the next count since the electrons are injected from the emitter constantly. Therefore, a properly designed switch on the base is necessary for better control of the SPAT.

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vii
表目錄 xi
第一章 前言 1
1.1 研究背景與發展 1
1.2 研究動機 2
第二章 CMOS單光子崩潰偵測器原理及特性簡介 4
2.1 光偵測原理 4
2.2 單光子崩潰二極體基本特性 8
2.2.1 SPAD基本特性 8
2.2.2 冷卻電路(Quenching circuit) 11
2.2.3 雜訊來源 12
2.3 BJT電晶體基本特性 14
2.3.1 BJT的BVCBO與BVCEO 14
2.3.2 遲滯現象(Hysteresis) 15
第三章 設計與模擬 17
3.1 設計流程 17
3.1.1 SPAT in standard CMOS process 18
3.2 光電晶體結構設計 19
3.2.1 VBJT 19
3.2.2 VBJT+NMOS 26
3.3 冷卻電路的設計 29
3.3.1 AQC模擬環境 29
3.3.2 元件模型設計 31
3.3.3 AQC行為分析 32
3.3.4 Hold-off 電路行為分析 33
3.3.5 製程變異(Process corner) 36
3.4 元件佈局設計 39
3.5 電路佈局設計 45
第四章 量測與討論 46
4.1 量測儀器簡介 46
4.2 量測環境 47
4.2.1 電流對電壓量測 47
4.2.2 計數量測 47
4.2.3 響應度量測 48
4.3 量測結果 48
4.3.1 晶片量測圖 48
4.3.2 VBJT的I-V特性量測 49
4.3.3 暗計數量測 54
4.3.4 光響應度量測 56
4.3.5 AQC量測 61
第五章 結果分析與討論 62
5.1 暗計數探討 62
5.1.1 延遲時間不夠長 62
5.1.2 基極中的電洞消失緩慢 64
5.1.2.1 VBJT的基極電位量測 64
5.2 電路設計改良 66
5.2.1 冷卻電路設計改良 66
5.3 基極端點漏電流對崩潰電壓的影響 67
5.3.1 電容浮接 67
5.3.2 電容後接一小尺寸NMOS 68
5.4 以基極和集極的接面做SPAD 72
5.5 P型井深度模擬與量測比較 74
第六章 結論&後續建議 75
參考文獻 76

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