本論文使用了四種不同磊晶結構的氮化鎵（GaN）矽基板試片，並採用氧化銦錫（ITO）作為p型氮化鎵（p-GaN）閘極之歐姆接觸金屬，製作出了p型氮化鎵高電子遷移率電晶體（p-GaN gate HEMTs）。四種磊晶結構之主要差別為氮化鋁鎵（AlGaN）層的厚度、表面p-GaN的鎂摻雜濃度、於p-GaN與AlGaN之間添加一層未摻雜氮化鎵（u-GaN）。四種試片所製作出的元件之臨界電壓（threshold voltage）由小至大分別為0.1 V、0.2 V、1.5 V、2.0 V，實驗中發現了藉由減少AlGaN層之厚度，可以有效的提升臨界電壓。再進一步對其中臨界電壓最高的元件進行崩潰電壓的量測，於汲極電流達1 mA/mm之崩潰電壓為1790 V。而增加表面p-GaN之摻雜濃度，雖然會使得閘極的漏電流較大，但可以有效的提升閘極可靠度，其閘極所能承受之電壓應力達39.0 V，展現良好的閘極穩定度。透過在p-GaN與AlGaN之間加入一層u-GaN，可以防止因過度蝕刻而損害到2DEG，如此一來能提升元件的電性，其汲極飽和電流可由42 mA/mm提升至188 mA/mm。此外，與傳統之Ni/Au蕭特基閘極相比，ITO閘極展現了較佳的可靠度，期待未來能應用於高功率領域中。

In this work, we demonstrate ITO electrode p-GaN gate high electron mobility transistors (HEMTs) with four different GaN-on-Si epitaxial structures. The structural differences between these four substrates are the thickness of the aluminum gallium nitride (AlGaN) layer, the magnesium doping concentration of the p-GaN layer, and the insertion of an undoped gallium nitride (u-GaN) layer between p-GaN and AlGaN. The four fabricated devices showed threshold voltages of 0.1 V, 0.2 V, 1.5 V, and 2.0 V, respectively. The threshold voltage can be increased by reducing the AlGaN layer thickness. The device with the highest threshold voltage exhibits a high breakdown voltage of 1790 V at a drain current of 1 mA/mm. While increasing the doping concentration of the p-GaN layer would increase the gate leakage current, it could improve the reliability of the gate electrodes. From a step-stress measurement, the analyzed devices demonstrated a stable behavior up to VGS = 39.0 V, indicating excellent gate stability. From experimental observations, inserting a layer of u-GaN between p-GaN and AlGaN could prevent over-etching to the two-dimensional electron gas (2DEG), thus enhancing the output performance of the device, resulting in a saturation drain current increase from 42 mA/mm to 188 mA/mm. Compared with a conventional Ni/Au Schottky contact, our results on the ITO ohmic contact show better stability, which indicates the potential of the ITO p-GaN gate HEMTs for high power applications.

摘要 I
Abstract II
目錄 III
圖目錄 V
表目錄 VIII
第一章 序論 1
1.1 前言 1
1.2 文獻回顧 5
1.2.1 氮化鋁鎵/氮化鎵異質結構 5
1.2.2 氮化鋁鎵/氮化鎵高電子遷移率電晶體 5
1.2.3 p型氮化鎵高電子遷移率電晶體 7
1.2.4 p型氮化鎵閘極接觸金屬 9
1.3 研究方向與架構 12
1.3.1 研究方向 12
1.3.2 論文架構 12
第二章 原理簡介 13
2.1 氮化鎵材料特性 13
2.1.1 自發性極化（spontaneous polarization） 13
2.1.2 壓電極化（piezoelectric polarization） 14
2.1.3 氮化鋁鎵/氮化鎵異質結構 14
2.2 p型氮化鎵覆蓋層（cap layer） 15
2.3 p型氮化鎵蝕刻製程 16
2.4 p型氮化鎵閘極歐姆接觸 20
第三章 元件製作流程 22
3.1 晶圓之磊晶結構 22
3.2 p-GaN gate HEMT元件製作流程 24
3.2.1 試片清潔（sample cleaning） 24
3.2.2 對準記號蝕刻（alignment mark formation） 25
3.2.3 氧離子佈植隔離（oxygen ion implantation isolation）27
3.2.4 ITO薄膜沉積（ITO deposition） 28
3.2.5 ITO薄膜蝕刻（ITO etching） 29
3.2.6 p-GaN蝕刻（p-GaN etching） 30
3.2.7 源極/汲極歐姆接觸金屬（source/drain ohmic contact） 31
3.2.8 襯墊金屬（pad metal） 33
3.2.9 鈍化層沉積（surface passivation）與第二層襯墊金屬 34
3.3 元件尺寸與影像 36
3.3.1 元件規格 36
3.3.2 元件俯視圖 37
3.3.3 元件TEM（transmission electron microscope）影像 39
第四章 元件量測與結果分析 40
4.1 TLM（transfer length method）測試結構量測 40
4.1.1 2DEG TLM量測 40
4.1.2 ITO/p-GaN TLM量測 45
4.2 HEMT直流特性量測 49
4.2.1 閘極與源極間P-N接面量測 49
4.2.2 相同Lgd之汲極電流對閘極電壓特性曲線（Id-Vg） 50
4.2.3 相同Lgd之汲極電流對汲極電壓特性曲線（Id-Vd） 55
4.2.4 不同Lgd之汲極電流對閘極電壓特性曲線（Id-Vg） 61
4.2.5 不同Lgd之汲極電流對汲極電壓特性曲線（Id-Vd） 63
4.3 HEMT水平崩潰電壓（breakdown）量測 66
4.4 HEMT閘極可靠度量測 70
4.4.1 閘極崩潰電壓（gate breakdown）量測 71
4.4.1.1 ITO閘極與Ni/Au閘極HEMT之比較 73
4.4.1.2 四種晶圓ITO閘極HEMT之比較 75
4.4.2 HEMT閘極逐步電壓應力（gate step-stress）量測 79
4.4.2.1 ITO閘極與Ni/Au閘極HEMT之比較 81
4.4.2.2 四種晶圓ITO閘極HEMT之比較 84
第五章 結論與未來工作 89
參考文獻 90

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