|
[1] R. Cheung, Silicon Carbide Microelectromechanical Systems for Harsh Environments, Imperial College Press, 2006, p. 3. [2] A. Powell and L. Rowland, "SiC materials-progress, status, and potential roadblocks," Proceedings of the IEEE, vol. 90, no. 6, pp. 942 - 955, June 2002. [3] C. Zetterling, Process Technology for Silicon Carbide Devices, EMIS processing series IEEE, 2002. [4] B. Baliga, M.S. Adler, D.W. Oliver "Optimum semiconductors for power field effect transistors," IEEE Electron Device Letters, vol. 2, pp. 162 - 164, 1981. [5] J. Appels and H. Vaes, "High voltage thin layer devices (RESURF devices)," in 1979 International Electron Devices Meeting, Washington, DC, USA, 1979, pp. 238-241. [6] M. Imam, M. Quddus, J. Adams and Z. Hossain, "Efficacy of charge sharing in reshaping the surface electric field in high-voltage lateral RESURF devices," IEEE Transactions on Electron Devices, vol. 51, no. 1, pp. 141 - 148, 7 Jan. 2004 . [7] H. Vaes and J. Appels, "High voltage, high current lateral devices," in 1980 International Electron Devices Meeting, Washington, DC, USA, USA, 1980, pp. 87-90. [8] B. J. Baliga, Fundamentals of Power Semiconductor Devices, Springer Science + Business Media, LLC, 2008, p. 133. [9] F.C. Hsu and H.R. Grinolds, “Structure-enhanced MOSFET degradation due to hot-electron injection,” IEEE Electron Device Letters, vol. 5, no. 3, pp. 71-74, 1984.. [10] P. Moens, G.V. den bosch, G. Groeseneken,” Hot-carrier degradation phenomena in lateral and vertical DMOS transistors,” IEEE Trans. Electron Devices, vol. 51, no. 4, pp. 623-628, 2004. [11] C.M. Hu, C. Tam, F.C. Hsu, P.K. Ko, T.Y. Chan, K.W. Terrill, “Hot-electron-induced MOSFET degradation model, monitor, and improvement,” IEEE Journal of Solid-State Circuits, vol. 20, no. 1, pp. 295-305, 1985. [12] J.S. Brugler, P.G.A. Jespers, “Charge pumping in MOS devices,” IEEE Trans. Electron Devices, vol. 16, no.3, pp. 297-302, 1969 [13] A. Salinaro et al, "Charge pumping measurements on differently passivated lateral 4H-SiC MOSFETs," IEEE Trans. Electron Devices, vol. 62, no.1, pp. 155-163, Jan. 2015 [14] D. Okamoto, H. Yano, T. Hatayama, Y. Uraoka, and T. Fuyuki, “Analysis of anomalous charge-pumping characteristics on 4H-SiC MOSFETs,” IEEE Trans. Electron Devices, vol. 55, no. 8, pp. 2013–2020, Aug. 2008. [15] S.K. Cheng, et al, “A Novel 700V Deep Trench Isolated Double RESURF LDMOS with P-sink Layer,” in Proc. 29th Int. Symp. Power Semiconductor Devices and ICs, pp. 323-326, Sapporo, Japan, July 2017. [16] G. Pobegen, T. Aichinger, A. Salinaro, and T. Grasser, “Impact of hot carrier degradation and positive bias stress on lateral 4H-SiC nMOSFETs”, Materials Science Forum, vol. 778-780, pp. 959–962, 2014. [17] Chih-Chang Cheng, K.C. Tu, Tahui Wang, T.H. Hsieh, J.T. Tzeng, Y.C. Jong, R.S. Liou, Sam C. Pan, and S.L. Hsu, "Investigation of Hot Carrier Degradation Modes in LDMO5 by Using a Novel Three-Region Charge Pumping Technque," IEEE International Reliability Physics Symposium (IRPS), pp.334-337, 2006.. [18] M. Noborio, J. Suda, and T. Kimoto, “4H-SiC lateral double RESURF MOSFETs with low on resistance,” IEEE Trans. Electron Devices, vol. 54, no. 5, pp. 1216–1223, May 2007. [19] J. Weiße, C. Matthus, H. Schlichting, H. Mitlehner, T. Erlbacher, “ RESURF n-LDMOS Transistor for Advanced Integrated Circuits in 4H-SiC,” IEEE Transactions on Electron Devices, vol. 67, pp. 3278-3284, July 2020. [20] M. Noborio, J. Suda, and T. Kimoto, “Improved performance of 4HSiC double reduced surface field metal–oxide–semiconductor field-effect transistors by increasing RESURF doses,” Appl. Phys. Express, vol. 1, no. 10, p. 101 403, 2008. |