在設計嵌入式系統時，用導線來連接元件間的針腳，往往是最容易出錯的步驟。雖然元件大
多支援標準的通訊介面，得以互相連接，設計師仍然有機會忽略接線邏輯之外的細節，如電
壓、頻率、其他電路特性與參數設定。兩介面之間不相容時，也許可以透過新增轉換器來加
以解決，但是目前鮮有正規的轉換方法可以套用，仍需仰賴設計師的經驗。此外，硬體設計
只要有一個小錯誤，就可能導致整塊電路板無法發揮應有的功能。若是每次修改設計都須重
新製板，將負擔大量額外成本與製作時間，導致超出預算及開發時程延宕； 而若不修改硬體
電路，選擇將錯就錯的改寫韌體以符合硬體錯誤，將造成韌體無法重覆使用，進而增加程式
碼維護的困擾。
為了解決這些問題，我們提出一種以圖形重構實現嵌入式元件連接自動化的演算法。透
過圖形建立元件間相互連結的需求模型，並定義圖形重構的規則，得以將不完整的電路自動
改寫成為一個完整、正確的電路圖。相較於其他介面合成工具的作法，此工具的一大優勢在
於尊重設計師指定的局部手動接線，在配合設計師指定的方式的前提下，自動填入剩餘所需
的部分，而非由合成工具硬性決定所有的連接方式。實驗結果顯示，我們的演算法不只能夠
正確填入所有必需連接的導線，還能最佳化資源運用的分配。

One of the most error-prone steps in designing embedded hardware is to connect the ports between
components that need to communicate with each other. Although standards exist to facilitate connection,
one frequent trap is that designer may correctly connect the ports by wire but neglects to check
the properties at all pertinent levels of abstraction, including voltage, speed, and other settings. What
is less obvious is how to resolve incompatibility by inserting interfacing hardware. One minor mistake
can render the entire board inoperable, and corrections can entail either re-fabricating hardware
that can be costly or firmware workarounds that are difficult to maintain and reuse.
To address these problems, we propose an automatic way to realize the intercomponent connections
by a graph rewrite algorithm. We model the requirements on intercomponent connection using
a graph model and propose graph rewrite rules to enable automatic transformation of an incomplete
schematic into a complete and correct one. Unlike traditional interface synthesis, our approach still
gives designers full control by allowing them to manually designate certain wires and fills in the missing
details accordingly, instead of synthesizing the entire connection. Experimental results show our
algorithm to not only generate correct connections but also even optimize the connection by taking
advantage of existing features whenever possible.

Contents i
Acknowledgments vi
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Signal Misconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.3 Compatible Signals with Incompatible Levels . . . . . . . . . . . . . . . . . 3
1.1.4 Resolving Incompatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.1 Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.2 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Related Work 9
2.1 Interface Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Graph Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Existing Libraries for Graph Rewrite . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Methodology 12
3.1 Overview of Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.1 Incomplete Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.1 Completed Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.2 Modified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Interface Realization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.1 Configuration of Ports and Logic Pin . . . . . . . . . . . . . . . . . . . . . 19
3.4.2 Stability of Design Modification . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.3 Satisfibility of Resource Allocation . . . . . . . . . . . . . . . . . . . . . . 21
3.4.4 Validity Ensuring and Conversion of Connections . . . . . . . . . . . . . . . 21
4 Formulation 23
4.1 Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.1 Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.2 Property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.3 Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 Graph Rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2.1 Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2.2 Graph Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3 Illustrative Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5 Technical Approach 31
5.1 Graph Rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1.1 Procedure Flow and Structure of Graph Rewrite . . . . . . . . . . . . . . . . 31
5.2 Rewriting Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3 Matching LHS Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.4 Rewriting with RHS Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.5 Termination and Ambiguity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6 Evaluation 50
6.1 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1.1 Inserting Glue Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1.2 Reallocating Resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.2 Comparing to Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.2.1 AutoFritz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.2.2 EDAsolver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7 Conclusions and Future Work 53
7.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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